From patchwork Fri Aug 20 11:14:54 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chun-Jie Chen X-Patchwork-Id: 12449073 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 82929C4338F for ; Fri, 20 Aug 2021 11:29:26 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 56AB061040 for ; Fri, 20 Aug 2021 11:29:26 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 56AB061040 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=+92mUdXOK9fZSREY0OBsx2hkKzsyxP/0/7/56vKTXtU=; b=UgHZfZi0iYzlbK rUfVioTVfo2otqDL/rJdWvVE3LZIk391EZvb7ZdqfzZ2lCQadBni+99duX9UZo51147D/+WuAP1/+ j38UphYfq5FJRDSnvg134Zy/zAl3SWyQJzvUDX840l8soDn/dJGkgdB0RdfAeIswJCArgrESBHciF vo8g0BoeRsTuPIGFK76zcKGhZWErv93WF2488cWl74bWnb3hj5Ee7drC0ZIuhGkHuhEfDCyRi8qmZ wp1gKUBB+p5pZdV4hQ1BDWMvluuvm9QsH01VyE0r32NzvlJMMUE3ir+HFeuw7ppceexe7G38Xr7MJ 1TajdPyogn4X7mIAN6vg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mH2fG-00AqFI-OC; Fri, 20 Aug 2021 11:26:23 +0000 Received: from mailgw01.mediatek.com ([216.200.240.184]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mH2Wk-00AmAP-OU; Fri, 20 Aug 2021 11:17:38 +0000 X-UUID: 793919dd03e0415bb90c2f6c1236f85f-20210820 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=TDgxs+Bbg18HokutrT+1qwu6RkfS7xc7RhzCpXihIVY=; b=THRs8bIrd1/fC5CRJlcL1h0FxIXkqEjXcMunABF9nTkDZHUjfJQrvhvC0BkiYz8FolspxwfOzROGeaJHR8TIlPcXJ56dIR5EIGmhRm38X3H8q0x5yCsv1ntKbjGcJO+Cz12IaTe4yxxc624ROG2XIAxXMkTYKvKOVJmv01906rY=; X-UUID: 793919dd03e0415bb90c2f6c1236f85f-20210820 Received: from mtkcas68.mediatek.inc [(172.29.94.19)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 618123276; Fri, 20 Aug 2021 04:17:33 -0700 Received: from mtkmbs07n1.mediatek.inc (172.21.101.16) by MTKMBS62N2.mediatek.inc (172.29.193.42) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 20 Aug 2021 04:17:31 -0700 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 20 Aug 2021 19:17:30 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 20 Aug 2021 19:17:30 +0800 From: Chun-Jie Chen To: Matthias Brugger , Stephen Boyd , Nicolas Boichat , Rob Herring CC: , , , , , , , Chun-Jie Chen Subject: [v2 14/24] clk: mediatek: Add MT8195 mfgcfg clock support Date: Fri, 20 Aug 2021 19:14:54 +0800 Message-ID: <20210820111504.350-15-chun-jie.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210820111504.350-1-chun-jie.chen@mediatek.com> References: <20210820111504.350-1-chun-jie.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210820_041734_869001_25C390C9 X-CRM114-Status: GOOD ( 15.91 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add MT8195 mfg clock controller which provides clock gate control for Main Frame Graphic. Signed-off-by: Chun-Jie Chen --- drivers/clk/mediatek/Makefile | 2 +- drivers/clk/mediatek/clk-mt8195-mfg.c | 47 +++++++++++++++++++++++++++ 2 files changed, 48 insertions(+), 1 deletion(-) create mode 100644 drivers/clk/mediatek/clk-mt8195-mfg.c diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index 84d315a6b3e4..042db433245a 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -81,6 +81,6 @@ obj-$(CONFIG_COMMON_CLK_MT8192_SCP_ADSP) += clk-mt8192-scp_adsp.o obj-$(CONFIG_COMMON_CLK_MT8192_VDECSYS) += clk-mt8192-vdec.o obj-$(CONFIG_COMMON_CLK_MT8192_VENCSYS) += clk-mt8192-venc.o obj-$(CONFIG_COMMON_CLK_MT8195) += clk-mt8195-apmixedsys.o clk-mt8195-topckgen.o clk-mt8195-peri_ao.o clk-mt8195-infra_ao.o clk-mt8195-cam.o \ - clk-mt8195-ccu.o clk-mt8195-img.o clk-mt8195-ipe.o + clk-mt8195-ccu.o clk-mt8195-img.o clk-mt8195-ipe.o clk-mt8195-mfg.o obj-$(CONFIG_COMMON_CLK_MT8516) += clk-mt8516.o obj-$(CONFIG_COMMON_CLK_MT8516_AUDSYS) += clk-mt8516-aud.o diff --git a/drivers/clk/mediatek/clk-mt8195-mfg.c b/drivers/clk/mediatek/clk-mt8195-mfg.c new file mode 100644 index 000000000000..0a81fe1fe50e --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8195-mfg.c @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// +// Copyright (c) 2021 MediaTek Inc. +// Author: Chun-Jie Chen + +#include "clk-gate.h" +#include "clk-mtk.h" + +#include +#include +#include + +static const struct mtk_gate_regs mfg_cg_regs = { + .set_ofs = 0x4, + .clr_ofs = 0x8, + .sta_ofs = 0x0, +}; + +#define GATE_MFG(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &mfg_cg_regs, _shift, &mtk_clk_gate_ops_setclr) + +static const struct mtk_gate mfg_clks[] = { + GATE_MFG(CLK_MFG_BG3D, "mfg_bg3d", "top_mfg_core_tmp", 0), +}; + +static const struct mtk_clk_desc mfg_desc = { + .clks = mfg_clks, + .num_clks = ARRAY_SIZE(mfg_clks), +}; + +static const struct of_device_id of_match_clk_mt8195_mfg[] = { + { + .compatible = "mediatek,mt8195-mfgcfg", + .data = &mfg_desc, + }, { + /* sentinel */ + } +}; + +static struct platform_driver clk_mt8195_mfg_drv = { + .probe = mtk_clk_simple_probe, + .driver = { + .name = "clk-mt8195-mfg", + .of_match_table = of_match_clk_mt8195_mfg, + }, +}; +builtin_platform_driver(clk_mt8195_mfg_drv);