From patchwork Tue Aug 24 13:24:59 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandru Elisei X-Patchwork-Id: 12455009 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DD88BC4338F for ; Tue, 24 Aug 2021 13:26:18 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B045160FD8 for ; Tue, 24 Aug 2021 13:26:18 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org B045160FD8 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:To :From:Reply-To:Cc:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=ephkQ1visdWUn775aEssC7GUQyHR+1lrreUieIa0X+c=; b=39wRPnjlzUG7UI soERPZVOc7vNS0Ie4U3zAqRo1IVzIyoeMDJbIZqKUKuB/z+vBXM3Zt8yUYcCtEbmaGaTMNmk7Q45T S+RC6vXQS/bRFGYBgdJ/V9wrn9jS2hK1AEzlRyTAiFG1Juz32nB4nptZBDPP11RQBEooZ+uKv7U3i 20t7HXvHU4rhufTsW6mfhdSx8AkcvGupDkI5/PBw3kD63qmJiLUW8twezFaszoFIMP9vZOwOzsP1o CkIHn2aXHI+bw/+02Et8cEyCdsi88o5TWhSYqyPw7UPbhajc5XTyOPprcCn2Hq9cHr4O8c3UHrC1M klHIwqD8rTIcABwvhBjA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mIWPQ-003De1-Nz; Tue, 24 Aug 2021 13:24:08 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mIWPJ-003Db4-Rs for linux-arm-kernel@lists.infradead.org; Tue, 24 Aug 2021 13:24:07 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id CDB001042; Tue, 24 Aug 2021 06:23:47 -0700 (PDT) Received: from monolith.cable.virginm.net (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 9F3853F5A1; Tue, 24 Aug 2021 06:23:46 -0700 (PDT) From: Alexandru Elisei To: maz@kernel.org, james.morse@arm.com, suzuki.poulose@arm.com, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, broonie@kernel.org Subject: [PATCH] arm64: Do not trap PMSNEVFR_EL1 Date: Tue, 24 Aug 2021 14:24:59 +0100 Message-Id: <20210824132459.562923-1-alexandru.elisei@arm.com> X-Mailer: git-send-email 2.33.0 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210824_062402_020168_3553FDE1 X-CRM114-Status: GOOD ( 18.47 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Commit 31c00d2aeaa2 ("arm64: Disable fine grained traps on boot") zeroed the fine grained trap registers to prevent unwanted register traps from occuring. However, for the PMSNEVFR_EL1 register, the corresponding HDFGRTR_EL2.nPMSNEVFR_EL1 field must be 1 to disable trapping. Set the field to 1 if FEAT_SPEv1p2 is detected. Fixes: 31c00d2aeaa2 ("arm64: Disable fine grained traps on boot") Signed-off-by: Alexandru Elisei --- Based on v5.14-rc7. Also, we could write 1 << 62 to HDFGRTR_EL2 unconditionally since the field is RAZ/WI if !FEAT_SPEv1p2. I don't have a strong preference for either approaches, but I chose this implementation because it's clearer (even though it's more verbose and it's one extra trap on NV). Tested on the model, using boot-wrapper built from commit 5cd6238ec4ef ("aarch32: fix .globl replacement"). Without this patch, in NVHE mode, the model freezes when I try to read PMSNEVFR_EL1. With this patch, the model doesn't hang when I read the register, but it hangs when I write to it. I've gone throught the pseudocode for reading and writing to PMSNEVFR_EL1 and from what I can tell nothing should be trapping the accesses. On top of that, this is what I tried on the model with this patch applied: 1. VHE mode, I can read and write to PMSNEVFR_EL1 without any issues, so the hang is not caused by an incorrect EL3 configuration. 2. NVHE mode, I can read and write just fine to *PMSEVFR_EL1*, so the hang is not caused by an EL2 trap that affects the rest of the profiling control registers. I have tried printing the HDFGRTR_EL2 value in this situation using semihosting, the value is what it is programmed by __init_el2_fgt (that is, 1 << 62). At this point, I am inclined to think it's a model bug because reading works, but writing causes a hang and that looks very suspicious to me. I'm going to open a model bug internally and see what comes of it. arch/arm64/include/asm/el2_setup.h | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el2_setup.h index b83fb24954b7..8a9adb2039fd 100644 --- a/arch/arm64/include/asm/el2_setup.h +++ b/arch/arm64/include/asm/el2_setup.h @@ -149,7 +149,16 @@ ubfx x1, x1, #ID_AA64MMFR0_FGT_SHIFT, #4 cbz x1, .Lskip_fgt_\@ - msr_s SYS_HDFGRTR_EL2, xzr + mov x0, xzr + mrs x1, id_aa64dfr0_el1 + ubfx x1, x1, #ID_AA64DFR0_PMSVER_SHIFT, #4 + cmp x1, #3 + b.lt .Lset_fgt_\@ + /* Set HDFGRTR_EL2.nPMSNEVFR_EL1 to disable the register trap */ + orr x0, x0, #(1 << 62) + +.Lset_fgt_\@: + msr_s SYS_HDFGRTR_EL2, x0 msr_s SYS_HDFGWTR_EL2, xzr msr_s SYS_HFGRTR_EL2, xzr msr_s SYS_HFGWTR_EL2, xzr