| Message ID | 20210825011120.30481-2-chun-jie.chen@mediatek.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Update MT8192 Clock Setting | expand |
Hi Chun-Jie,
thanks for the patch! However, can you please improve the commit message? Here's
a possible suggestion:
When the initial devicetree for mt8192 was added in 48489980e27e ("arm64:
dts: Add Mediatek SoC MT8192 and evaluation board dts and Makefile"), the
clock driver for mt8192 was not yet upstream, so the clock property nodes
were set to the clk26m clock as a placeholder.
Given that the clock driver has since been added through 710573dee31b ("clk:
mediatek: Add MT8192 basic clocks support"), as well as its dt-bindings
through f35f1a23e0e1 ("clk: mediatek: Add dt-bindings of MT8192 clocks") and
devicetree nodes through 5d2b897bc6f5 ("arm64: dts: mediatek: Add mt8192
clock controllers"), fix the systimer clock property to point to the actual
clock.
Then you could use the same message for the other commits, just updating which
clock is being fixed in the last sentence there. With that improved commit
message:
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Thanks,
Nícolas
>
> Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index c7c7d4e017ae..2b63d2ea6cb6 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -312,7 +312,7 @@
> "mediatek,mt6765-timer";
> reg = <0 0x10017000 0 0x1000>;
> interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH 0>;
> - clocks = <&clk26m>;
> + clocks = <&topckgen CLK_TOP_CSW_F26M_D2>;
> clock-names = "clk13m";
> };
>
> --
> 2.18.0
>
>
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index c7c7d4e017ae..2b63d2ea6cb6 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -312,7 +312,7 @@ "mediatek,mt6765-timer"; reg = <0 0x10017000 0 0x1000>; interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&clk26m>; + clocks = <&topckgen CLK_TOP_CSW_F26M_D2>; clock-names = "clk13m"; };
update systimer clock to the real one. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)