| Message ID | 20210825144833.7757-6-jason-jh.lin@mediatek.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add Mediatek Soc DRM (vdosys0) support for mt8195 | expand |
Hi, Jason: jason-jh.lin <jason-jh.lin@mediatek.com> 於 2021年8月25日 週三 下午10:48寫道： > > 1. Add mt8195 SoC binding to AAL, CCORR, COLOR, DITHER, GAMMA, MERGE, > MUTEX, OVL and RDMA yaml schema. > > 2. Add MERGE additional property description for mt8195 > - async clock > - fifo setting enable > - reset controller I would like you to separate merge additional property description to an independent patch. Regards, Chun-Kuang. > > Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com> > --- > .../display/mediatek/mediatek,aal.yaml | 1 + > .../display/mediatek/mediatek,ccorr.yaml | 2 ++ > .../display/mediatek/mediatek,color.yaml | 1 + > .../display/mediatek/mediatek,dither.yaml | 5 +++ > .../display/mediatek/mediatek,gamma.yaml | 5 +++ > .../display/mediatek/mediatek,merge.yaml | 32 +++++++++++++++++++ > .../display/mediatek/mediatek,mutex.yaml | 2 ++ > .../display/mediatek/mediatek,ovl.yaml | 5 +++ > .../display/mediatek/mediatek,rdma.yaml | 2 ++ > 9 files changed, 55 insertions(+) > > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml > index faa764c12dfc..1599184a4dd1 100644 > --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml > @@ -26,6 +26,7 @@ properties: > - enum: > - mediatek,mt2712-disp-aal > - mediatek,mt8183-disp-aal > + - mediatek,mt8195-disp-aal > - enum: > - mediatek,mt8173-disp-aal > > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml > index e848879d755c..f9b697604ab9 100644 > --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml > @@ -22,6 +22,8 @@ properties: > oneOf: > - items: > - const: mediatek,mt8183-disp-ccorr > + - items: > + - const: mediatek,mt8195-disp-ccorr > > reg: > maxItems: 1 > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml > index 019fc09bbddd..563755095a4f 100644 > --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml > @@ -36,6 +36,7 @@ properties: > - items: > - enum: > - mediatek,mt8183-disp-color > + - mediatek,mt8195-disp-color > - enum: > - mediatek,mt8173-disp-color > reg: > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml > index 8e7c87c39f9c..b6f57243270c 100644 > --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml > @@ -23,6 +23,11 @@ properties: > oneOf: > - items: > - const: mediatek,mt8183-disp-dither > + - items: > + - enum: > + - mediatek,mt8195-disp-dither > + - enum: > + - mediatek,mt8183-disp-dither > > reg: > maxItems: 1 > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml > index 8fa1b373a8da..ab1e18da6bed 100644 > --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml > @@ -24,6 +24,11 @@ properties: > - const: mediatek,mt8173-disp-gamma > - items: > - const: mediatek,mt8183-disp-gamma > + - items: > + - enum: > + - mediatek,mt8195-disp-gamma > + - enum: > + - mediatek,mt8183-disp-gamma > > reg: > maxItems: 1 > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml > index ca51a4c4a8c7..b15c6e17b421 100644 > --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml > @@ -22,6 +22,8 @@ properties: > oneOf: > - items: > - const: mediatek,mt8173-disp-merge > + - items: > + - const: mediatek,mt8195-disp-merge > > reg: > maxItems: 1 > @@ -37,6 +39,19 @@ properties: > clocks: > items: > - description: MERGE Clock > + - description: MERGE Async Clock > + Controlling the synchronous process between MERGE and other display function > + blocks cross clock domain. > + > + mediatek,merge-fifo-en: > + description: > + The setting of merge fifo is mainly provided for the display latency buffer. > + to ensure that the back-end panel display data will not be underrun, > + a little more data is needed in the fifo. According to the merge fifo settings, > + when the water level is detected to be insufficient, it will trigger RDMA sending > + ultra and preulra command to SMI to speed up the data rate. > + type: boolean > + > > mediatek,gce-client-reg: > description: > @@ -47,6 +62,10 @@ properties: > $ref: /schemas/types.yaml#/definitions/phandle-array > maxItems: 1 > > + resets: > + description: reset controller > + See Documentation/devicetree/bindings/reset/reset.txt for details. > + > required: > - compatible > - reg > @@ -64,3 +83,16 @@ examples: > power-domains = <&spm MT8173_POWER_DOMAIN_MM>; > clocks = <&mmsys CLK_MM_DISP_MERGE>; > }; > + > + merge5: disp_vpp_merge5@1c110000 { > + compatible = "mediatek,mt8195-disp-merge"; > + reg = <0 0x1c110000 0 0x1000>; > + interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH 0>; > + clocks = <&vdosys1 CLK_VDO1_VPP_MERGE4>, > + <&vdosys1 CLK_VDO1_MERGE4_DL_ASYNC>; > + clock-names = "merge","merge_async"; > + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; > + mediatek,gce-client-reg = <&gce1 SUBSYS_1c11XXXX 0x0000 0x1000>; > + mediatek,merge-fifo-en = <1>; > + resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE4_DL_ASYNC>; > + }; > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml > index 939dff14d989..db9db182318d 100644 > --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml > @@ -31,6 +31,8 @@ properties: > - const: mediatek,mt8173-disp-mutex > - items: > - const: mediatek,mt8183-disp-mutex > + - items: > + - const: mediatek,mt8195-disp-mutex > > reg: > maxItems: 1 > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml > index a0c29cd3377a..5008f900d81f 100644 > --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml > @@ -32,6 +32,11 @@ properties: > - mediatek,mt2712-disp-ovl > - enum: > - mediatek,mt2701-disp-ovl > + - items: > + - enum: > + - mediatek,mt8195-disp-ovl > + - enum: > + - mediatek,mt8183-disp-ovl > > reg: > maxItems: 1 > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml > index 837659ab4ebd..806437166e3c 100644 > --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml > @@ -28,6 +28,8 @@ properties: > - const: mediatek,mt8173-disp-rdma > - items: > - const: mediatek,mt8183-disp-rdma > + - items: > + - const: mediatek,mt8195-disp-rdma > - items: > - enum: > - mediatek,mt7623-disp-rdma > -- > 2.18.0 >
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml index faa764c12dfc..1599184a4dd1 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml @@ -26,6 +26,7 @@ properties: - enum: - mediatek,mt2712-disp-aal - mediatek,mt8183-disp-aal + - mediatek,mt8195-disp-aal - enum: - mediatek,mt8173-disp-aal diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml index e848879d755c..f9b697604ab9 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml @@ -22,6 +22,8 @@ properties: oneOf: - items: - const: mediatek,mt8183-disp-ccorr + - items: + - const: mediatek,mt8195-disp-ccorr reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml index 019fc09bbddd..563755095a4f 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml @@ -36,6 +36,7 @@ properties: - items: - enum: - mediatek,mt8183-disp-color + - mediatek,mt8195-disp-color - enum: - mediatek,mt8173-disp-color reg: diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml index 8e7c87c39f9c..b6f57243270c 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml @@ -23,6 +23,11 @@ properties: oneOf: - items: - const: mediatek,mt8183-disp-dither + - items: + - enum: + - mediatek,mt8195-disp-dither + - enum: + - mediatek,mt8183-disp-dither reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml index 8fa1b373a8da..ab1e18da6bed 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml @@ -24,6 +24,11 @@ properties: - const: mediatek,mt8173-disp-gamma - items: - const: mediatek,mt8183-disp-gamma + - items: + - enum: + - mediatek,mt8195-disp-gamma + - enum: + - mediatek,mt8183-disp-gamma reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml index ca51a4c4a8c7..b15c6e17b421 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml @@ -22,6 +22,8 @@ properties: oneOf: - items: - const: mediatek,mt8173-disp-merge + - items: + - const: mediatek,mt8195-disp-merge reg: maxItems: 1 @@ -37,6 +39,19 @@ properties: clocks: items: - description: MERGE Clock + - description: MERGE Async Clock + Controlling the synchronous process between MERGE and other display function + blocks cross clock domain. + + mediatek,merge-fifo-en: + description: + The setting of merge fifo is mainly provided for the display latency buffer. + to ensure that the back-end panel display data will not be underrun, + a little more data is needed in the fifo. According to the merge fifo settings, + when the water level is detected to be insufficient, it will trigger RDMA sending + ultra and preulra command to SMI to speed up the data rate. + type: boolean + mediatek,gce-client-reg: description: @@ -47,6 +62,10 @@ properties: $ref: /schemas/types.yaml#/definitions/phandle-array maxItems: 1 + resets: + description: reset controller + See Documentation/devicetree/bindings/reset/reset.txt for details. + required: - compatible - reg @@ -64,3 +83,16 @@ examples: power-domains = <&spm MT8173_POWER_DOMAIN_MM>; clocks = <&mmsys CLK_MM_DISP_MERGE>; }; + + merge5: disp_vpp_merge5@1c110000 { + compatible = "mediatek,mt8195-disp-merge"; + reg = <0 0x1c110000 0 0x1000>; + interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&vdosys1 CLK_VDO1_VPP_MERGE4>, + <&vdosys1 CLK_VDO1_MERGE4_DL_ASYNC>; + clock-names = "merge","merge_async"; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; + mediatek,gce-client-reg = <&gce1 SUBSYS_1c11XXXX 0x0000 0x1000>; + mediatek,merge-fifo-en = <1>; + resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE4_DL_ASYNC>; + }; diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml index 939dff14d989..db9db182318d 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml @@ -31,6 +31,8 @@ properties: - const: mediatek,mt8173-disp-mutex - items: - const: mediatek,mt8183-disp-mutex + - items: + - const: mediatek,mt8195-disp-mutex reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml index a0c29cd3377a..5008f900d81f 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml @@ -32,6 +32,11 @@ properties: - mediatek,mt2712-disp-ovl - enum: - mediatek,mt2701-disp-ovl + - items: + - enum: + - mediatek,mt8195-disp-ovl + - enum: + - mediatek,mt8183-disp-ovl reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml index 837659ab4ebd..806437166e3c 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml @@ -28,6 +28,8 @@ properties: - const: mediatek,mt8173-disp-rdma - items: - const: mediatek,mt8183-disp-rdma + - items: + - const: mediatek,mt8195-disp-rdma - items: - enum: - mediatek,mt7623-disp-rdma
1. Add mt8195 SoC binding to AAL, CCORR, COLOR, DITHER, GAMMA, MERGE, MUTEX, OVL and RDMA yaml schema. 2. Add MERGE additional property description for mt8195 - async clock - fifo setting enable - reset controller Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com> --- .../display/mediatek/mediatek,aal.yaml | 1 + .../display/mediatek/mediatek,ccorr.yaml | 2 ++ .../display/mediatek/mediatek,color.yaml | 1 + .../display/mediatek/mediatek,dither.yaml | 5 +++ .../display/mediatek/mediatek,gamma.yaml | 5 +++ .../display/mediatek/mediatek,merge.yaml | 32 +++++++++++++++++++ .../display/mediatek/mediatek,mutex.yaml | 2 ++ .../display/mediatek/mediatek,ovl.yaml | 5 +++ .../display/mediatek/mediatek,rdma.yaml | 2 ++ 9 files changed, 55 insertions(+)