| Message ID | 20210908060312.24007-8-jason-jh.lin@mediatek.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add Mediatek Soc DRM (vdosys0) support for mt8195 | expand |
Hi Jason, On Wed, 2021-09-08 at 14:03 +0800, jason-jh.lin wrote: > add MERGE additional properties description for mt8195: > 1. async clock > 2. fifo setting enable > 3. reset controller > > Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com> > --- > .../display/mediatek/mediatek,merge.yaml | 30 +++++++++++++++++++ > 1 file changed, 30 insertions(+) > > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml > index 75beeb207ceb..0fe204d9ad2c 100644 > --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml > @@ -38,6 +38,19 @@ properties: > clocks: > items: > - description: MERGE Clock > + - description: MERGE Async Clock > + Controlling the synchronous process between MERGE and other display > + function blocks cross clock domain. > + > + mediatek,merge-fifo-en: > + description: > + The setting of merge fifo is mainly provided for the display latency > + buffer to ensure that the back-end panel display data will not be > + underrun, a little more data is needed in the fifo. > + According to the merge fifo settings, when the water level is detected > + to be insufficient, it will trigger RDMA sending ultra and preulra > + command to SMI to speed up the data rate. > + type: boolean > > mediatek,gce-client-reg: > description: > @@ -50,6 +63,10 @@ properties: > $ref: /schemas/types.yaml#/definitions/phandle-array > maxItems: 1 > > + resets: > + description: reset controller > + See Documentation/devicetree/bindings/reset/reset.txt for details. From the example this looks like it could have a maxItems: 1. > + > required: > - compatible > - reg Should the resets property be required for "mediatek,mt8195-disp-merge"? > @@ -67,3 +84,16 @@ examples: > power-domains = <&spm MT8173_POWER_DOMAIN_MM>; > clocks = <&mmsys CLK_MM_DISP_MERGE>; > }; > + > + merge5: disp_vpp_merge5@1c110000 { > + compatible = "mediatek,mt8195-disp-merge"; > + reg = <0 0x1c110000 0 0x1000>; > + interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH 0>; > + clocks = <&vdosys1 CLK_VDO1_VPP_MERGE4>, > + <&vdosys1 CLK_VDO1_MERGE4_DL_ASYNC>; > + clock-names = "merge","merge_async"; > + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; > + mediatek,gce-client-reg = <&gce1 SUBSYS_1c11XXXX 0x0000 0x1000>; > + mediatek,merge-fifo-en = <1>; > + resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE4_DL_ASYNC>; > + }; regards Philipp
Hi Philipp, Thanks for the reviews. On Wed, 2021-09-08 at 08:39 +0200, Philipp Zabel wrote: > Hi Jason, > > On Wed, 2021-09-08 at 14:03 +0800, jason-jh.lin wrote: > > add MERGE additional properties description for mt8195: > > 1. async clock > > 2. fifo setting enable > > 3. reset controller > > > > Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com> > > --- > > .../display/mediatek/mediatek,merge.yaml | 30 > > +++++++++++++++++++ > > 1 file changed, 30 insertions(+) > > > > diff --git > > a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge > > .yaml > > b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge > > .yaml > > index 75beeb207ceb..0fe204d9ad2c 100644 > > --- > > a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge > > .yaml > > +++ > > b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge > > .yaml > > @@ -38,6 +38,19 @@ properties: > > clocks: > > items: > > - description: MERGE Clock > > + - description: MERGE Async Clock > > + Controlling the synchronous process between MERGE and > > other display > > + function blocks cross clock domain. > > + > > + mediatek,merge-fifo-en: > > + description: > > + The setting of merge fifo is mainly provided for the display > > latency > > + buffer to ensure that the back-end panel display data will > > not be > > + underrun, a little more data is needed in the fifo. > > + According to the merge fifo settings, when the water level > > is detected > > + to be insufficient, it will trigger RDMA sending ultra and > > preulra > > + command to SMI to speed up the data rate. > > + type: boolean > > > > mediatek,gce-client-reg: > > description: > > @@ -50,6 +63,10 @@ properties: > > $ref: /schemas/types.yaml#/definitions/phandle-array > > maxItems: 1 > > > > + resets: > > + description: reset controller > > + See Documentation/devicetree/bindings/reset/reset.txt for > > details. > > From the example this looks like it could have a maxItems: 1. OK, I think it could have a maxItems: 1 in mt8195 because merge1~megre5 only have one async clock. > > > + > > required: > > - compatible > > - reg > > Should the resets property be required for "mediatek,mt8195-disp- > merge"? I think the resets property is not the required propoerty. The reset controller is for async clock of MERGE module on vdosys1. MERGE module on vdosys0 doesn't have async clock, so it doesn't need to add the resets property. Regards, Jason-JH.Lin > > > @@ -67,3 +84,16 @@ examples: > > power-domains = <&spm MT8173_POWER_DOMAIN_MM>; > > clocks = <&mmsys CLK_MM_DISP_MERGE>; > > }; > > + > > + merge5: disp_vpp_merge5@1c110000 { > > + compatible = "mediatek,mt8195-disp-merge"; > > + reg = <0 0x1c110000 0 0x1000>; > > + interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH 0>; > > + clocks = <&vdosys1 CLK_VDO1_VPP_MERGE4>, > > + <&vdosys1 CLK_VDO1_MERGE4_DL_ASYNC>; > > + clock-names = "merge","merge_async"; > > + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; > > + mediatek,gce-client-reg = <&gce1 SUBSYS_1c11XXXX 0x0000 > > 0x1000>; > > + mediatek,merge-fifo-en = <1>; > > + resets = <&vdosys1 > > MT8195_VDOSYS1_SW0_RST_B_MERGE4_DL_ASYNC>; > > + }; > > regards > Philipp
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml index 75beeb207ceb..0fe204d9ad2c 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml @@ -38,6 +38,19 @@ properties: clocks: items: - description: MERGE Clock + - description: MERGE Async Clock + Controlling the synchronous process between MERGE and other display + function blocks cross clock domain. + + mediatek,merge-fifo-en: + description: + The setting of merge fifo is mainly provided for the display latency + buffer to ensure that the back-end panel display data will not be + underrun, a little more data is needed in the fifo. + According to the merge fifo settings, when the water level is detected + to be insufficient, it will trigger RDMA sending ultra and preulra + command to SMI to speed up the data rate. + type: boolean mediatek,gce-client-reg: description: @@ -50,6 +63,10 @@ properties: $ref: /schemas/types.yaml#/definitions/phandle-array maxItems: 1 + resets: + description: reset controller + See Documentation/devicetree/bindings/reset/reset.txt for details. + required: - compatible - reg @@ -67,3 +84,16 @@ examples: power-domains = <&spm MT8173_POWER_DOMAIN_MM>; clocks = <&mmsys CLK_MM_DISP_MERGE>; }; + + merge5: disp_vpp_merge5@1c110000 { + compatible = "mediatek,mt8195-disp-merge"; + reg = <0 0x1c110000 0 0x1000>; + interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&vdosys1 CLK_VDO1_VPP_MERGE4>, + <&vdosys1 CLK_VDO1_MERGE4_DL_ASYNC>; + clock-names = "merge","merge_async"; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; + mediatek,gce-client-reg = <&gce1 SUBSYS_1c11XXXX 0x0000 0x1000>; + mediatek,merge-fifo-en = <1>; + resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE4_DL_ASYNC>; + };
add MERGE additional properties description for mt8195: 1. async clock 2. fifo setting enable 3. reset controller Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com> --- .../display/mediatek/mediatek,merge.yaml | 30 +++++++++++++++++++ 1 file changed, 30 insertions(+)