diff mbox series

[v2,5/8] arm64: dts: s32g2: add serial/uart support

Message ID 20210908064528.922-6-clin@suse.com (mailing list archive)
State New, archived
Headers show
Series arm64: dts: initial NXP S32G2 support | expand

Commit Message

Chester Lin Sept. 8, 2021, 6:45 a.m. UTC 
Add serial/uart support for NXP S32G2 based on the information provided by
NXP's CodeAurora BSP.

Signed-off-by: Larisa Grigore <larisa.grigore@nxp.com>
Signed-off-by: Chester Lin <clin@suse.com>
---
Changes in v2:
- Add new Signed-off-by.
- Fix the copyright string.
- Remove aliases.
- Revise reg properties based on new cell size.

 arch/arm64/boot/dts/freescale/s32g2.dtsi | 25 ++++++++++++++++++++++++
 1 file changed, 25 insertions(+)
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
index 53b18671deec..59ea8a25aa4c 100644
--- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
@@ -3,6 +3,7 @@ 
  * NXP S32G2 SoC family
  *
  * Copyright (c) 2021 SUSE LLC
+ * Copyright (c) 2017-2021 NXP
  */
 
 #include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -84,6 +85,30 @@  soc {
 		#size-cells = <1>;
 		ranges = <0 0 0 0x80000000>;
 
+		uart0: serial@401c8000 {
+			compatible = "nxp,s32g2-linflexuart",
+				     "fsl,s32v234-linflexuart";
+			reg = <0x401c8000 0x3000>;
+			interrupts = <GIC_SPI 82 IRQ_TYPE_EDGE_RISING>;
+			status = "disabled";
+		};
+
+		uart1: serial@401cc000 {
+			compatible = "nxp,s32g2-linflexuart",
+				     "fsl,s32v234-linflexuart";
+			reg = <0x401cc000 0x3000>;
+			interrupts = <GIC_SPI 83 IRQ_TYPE_EDGE_RISING>;
+			status = "disabled";
+		};
+
+		uart2: serial@402bc000 {
+			compatible = "nxp,s32g2-linflexuart",
+				     "fsl,s32v234-linflexuart";
+			reg = <0x402bc000 0x3000>;
+			interrupts = <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>;
+			status = "disabled";
+		};
+
 		gic: interrupt-controller@50800000 {
 			compatible = "arm,gic-v3";
 			reg = <0x50800000 0x10000>,