diff mbox series

[3/5] arm64: mte: CPU feature detection for Asymm MTE

Message ID 20210913081424.48613-4-vincenzo.frascino@arm.com (mailing list archive)
State New, archived
Headers show
Series arm64: ARMv8.7-A: MTE: Add asymm mode support | expand

Commit Message

Vincenzo Frascino Sept. 13, 2021, 8:14 a.m. UTC
Add the cpufeature entries to detect the presence of Asymmetric MTE.

Note: The tag checking mode is initialized via cpu_enable_mte() ->
kasan_init_hw_tags() hence to enable it we require asymmetric mode
to be at least on the boot CPU. If the boot CPU does not have it, it is
fine for late CPUs to have it as long as the feature is not enabled
(ARM64_CPUCAP_BOOT_CPU_FEATURE).

Cc: Will Deacon <will@kernel.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Suzuki K Poulose <Suzuki.Poulose@arm.com>
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
---
 arch/arm64/kernel/cpufeature.c | 10 ++++++++++
 arch/arm64/tools/cpucaps       |  1 +
 2 files changed, 11 insertions(+)

Comments

Catalin Marinas Sept. 20, 2021, 3:31 p.m. UTC | #1
On Mon, Sep 13, 2021 at 09:14:22AM +0100, Vincenzo Frascino wrote:
> diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
> index f8a3067d10c6..a18774071a45 100644
> --- a/arch/arm64/kernel/cpufeature.c
> +++ b/arch/arm64/kernel/cpufeature.c
> @@ -2317,6 +2317,16 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
>  		.sign = FTR_UNSIGNED,
>  		.cpu_enable = cpu_enable_mte,
>  	},
> +	{
> +		.desc = "Asymmetric Memory Tagging Extension",

I'd give this a better name as it's not entirely clear what it does. In
the ARM ARM this is described as "asymmetric Tag Check Fault handling".
Maybe just rename it to "Asymmetric MTE Tag Check Fault". Similarly in
the Kconfig if you added one.

Otherwise:

Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Suzuki K Poulose Sept. 20, 2021, 3:41 p.m. UTC | #2
On 13/09/2021 09:14, Vincenzo Frascino wrote:
> Add the cpufeature entries to detect the presence of Asymmetric MTE.
> 
> Note: The tag checking mode is initialized via cpu_enable_mte() ->
> kasan_init_hw_tags() hence to enable it we require asymmetric mode
> to be at least on the boot CPU. If the boot CPU does not have it, it is
> fine for late CPUs to have it as long as the feature is not enabled
> (ARM64_CPUCAP_BOOT_CPU_FEATURE).
> 
> Cc: Will Deacon <will@kernel.org>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Suzuki K Poulose <Suzuki.Poulose@arm.com>
> Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>


> ---
>   arch/arm64/kernel/cpufeature.c | 10 ++++++++++
>   arch/arm64/tools/cpucaps       |  1 +
>   2 files changed, 11 insertions(+)
> 
> diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
> index f8a3067d10c6..a18774071a45 100644
> --- a/arch/arm64/kernel/cpufeature.c
> +++ b/arch/arm64/kernel/cpufeature.c
> @@ -2317,6 +2317,16 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
>   		.sign = FTR_UNSIGNED,
>   		.cpu_enable = cpu_enable_mte,
>   	},
> +	{
> +		.desc = "Asymmetric Memory Tagging Extension",
> +		.capability = ARM64_MTE_ASYMM,
> +		.type = ARM64_CPUCAP_BOOT_CPU_FEATURE,

FWIW, the selected type works for the described use case.

Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>

> +		.matches = has_cpuid_feature,
> +		.sys_reg = SYS_ID_AA64PFR1_EL1,
> +		.field_pos = ID_AA64PFR1_MTE_SHIFT,
> +		.min_field_value = ID_AA64PFR1_MTE_ASYMM,
> +		.sign = FTR_UNSIGNED,
> +	},
>   #endif /* CONFIG_ARM64_MTE */
>   	{
>   		.desc = "RCpc load-acquire (LDAPR)",
> diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps
> index 49305c2e6dfd..74a569bf52d6 100644
> --- a/arch/arm64/tools/cpucaps
> +++ b/arch/arm64/tools/cpucaps
> @@ -39,6 +39,7 @@ HW_DBM
>   KVM_PROTECTED_MODE
>   MISMATCHED_CACHE_TYPE
>   MTE
> +MTE_ASYMM
>   SPECTRE_V2
>   SPECTRE_V3A
>   SPECTRE_V4
>
diff mbox series

Patch

diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index f8a3067d10c6..a18774071a45 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -2317,6 +2317,16 @@  static const struct arm64_cpu_capabilities arm64_features[] = {
 		.sign = FTR_UNSIGNED,
 		.cpu_enable = cpu_enable_mte,
 	},
+	{
+		.desc = "Asymmetric Memory Tagging Extension",
+		.capability = ARM64_MTE_ASYMM,
+		.type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
+		.matches = has_cpuid_feature,
+		.sys_reg = SYS_ID_AA64PFR1_EL1,
+		.field_pos = ID_AA64PFR1_MTE_SHIFT,
+		.min_field_value = ID_AA64PFR1_MTE_ASYMM,
+		.sign = FTR_UNSIGNED,
+	},
 #endif /* CONFIG_ARM64_MTE */
 	{
 		.desc = "RCpc load-acquire (LDAPR)",
diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps
index 49305c2e6dfd..74a569bf52d6 100644
--- a/arch/arm64/tools/cpucaps
+++ b/arch/arm64/tools/cpucaps
@@ -39,6 +39,7 @@  HW_DBM
 KVM_PROTECTED_MODE
 MISMATCHED_CACHE_TYPE
 MTE
+MTE_ASYMM
 SPECTRE_V2
 SPECTRE_V3A
 SPECTRE_V4