[1/3] dt-bindings: interrupt-controller: Add SigmaStar SSD20xD gpi

Commit Message

Daniel Palmer Sept. 14, 2021, 10:04 a.m. UTC

Add a binding description for the SigmaStar GPIO interrupt
controller, gpi, found on the SSD201 and SSD202D.

Signed-off-by: Daniel Palmer <[e-mail]>
---
 .../sstar,ssd20xd-gpi.yaml                    | 53 +++++++++++++++++++
 MAINTAINERS                                   |  1 +
 2 files changed, 54 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/sstar,ssd20xd-gpi.yaml

Comments

Rob Herring (Arm) Sept. 21, 2021, 8:36 p.m. UTC | #1

On Tue, 14 Sep 2021 19:04:13 +0900, Daniel Palmer wrote:
> Add a binding description for the SigmaStar GPIO interrupt
> controller, gpi, found on the SSD201 and SSD202D.
> 
> Signed-off-by: Daniel Palmer <[e-mail]>
> ---
>  .../sstar,ssd20xd-gpi.yaml                    | 53 +++++++++++++++++++
>  MAINTAINERS                                   |  1 +
>  2 files changed, 54 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/interrupt-controller/sstar,ssd20xd-gpi.yaml
> 

Reviewed-by: Rob Herring <[e-mail]>

Patch

diff --git a/Documentation/devicetree/bindings/interrupt-controller/sstar,ssd20xd-gpi.yaml b/Documentation/devicetree/bindings/interrupt-controller/sstar,ssd20xd-gpi.yaml
new file mode 100644
index 000000000000..1f7e6c5fef52
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/sstar,ssd20xd-gpi.yaml
@@ -0,0 +1,53 @@ 
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/sstar,ssd20xd-gpi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: SigmaStar GPIO Interrupt Controller
+
+maintainers:
+  - Daniel Palmer <[e-mail]>
+
+description: |+
+  Newer SigmaStar SoCs from the SSD201/SSD202D have an extra
+  interrupt controller that is just for handling interrupts
+  on GPIOs and then routing a single interrupt to the peripheral
+  interrupt controller instead of only having a few interrupt
+  capable GPIOs that are routed directly to the peripheral
+  interrupt controller like older SoCs.
+
+properties:
+  compatible:
+    const: sstar,ssd20xd-gpi
+
+  interrupt-controller: true
+
+  "#interrupt-cells":
+    const: 2
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - interrupts
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/irq.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    interrupt-controller@207a00 {
+      compatible = "sstar,ssd20xd-gpi";
+      reg = <0x207a00 0x200>;
+      #interrupt-cells = <2>;
+      interrupt-controller;
+      interrupts-extended = <&intc_irq GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+    };
+...
diff --git a/MAINTAINERS b/MAINTAINERS
index eeb4c70b3d5b..3004c0f735b6 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2243,6 +2243,7 @@  T:	git git://github.com/linux-chenxing/linux.git
 F:	Documentation/devicetree/bindings/arm/mstar/*
 F:	Documentation/devicetree/bindings/clock/mstar,msc313-mpll.yaml
 F:	Documentation/devicetree/bindings/gpio/mstar,msc313-gpio.yaml
+F:	Documentation/devicetree/bindings/interrupt-controller/sstar,ssd20xd-gpi.yaml
 F:	arch/arm/boot/dts/mstar-*
 F:	arch/arm/mach-mstar/
 F:	drivers/clk/mstar/