| Message ID | 20210916181510.963449-6-oupton@google.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | KVM: arm64: Add idempotent controls to migrate guest counter | expand |
On Thu, Sep 16, 2021 at 11:15 AM Oliver Upton <oupton@google.com> wrote: > > Introduce a new cpucap to indicate if the system supports full enhanced > counter virtualization (i.e. ID_AA64MMFR0_EL1.ECV>=0x2). > > Signed-off-by: Oliver Upton <oupton@google.com> > --- > arch/arm64/include/asm/sysreg.h | 1 + > arch/arm64/kernel/cpufeature.c | 10 ++++++++++ > arch/arm64/tools/cpucaps | 1 + > 3 files changed, 12 insertions(+) > > diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h > index b268082d67ed..3fa6b091384d 100644 > --- a/arch/arm64/include/asm/sysreg.h > +++ b/arch/arm64/include/asm/sysreg.h > @@ -849,6 +849,7 @@ > #define ID_AA64MMFR0_ASID_8 0x0 > #define ID_AA64MMFR0_ASID_16 0x2 > > +#define ID_AA64MMFR0_ECV_PHYS 0x2 > #define ID_AA64MMFR0_TGRAN4_NI 0xf > #define ID_AA64MMFR0_TGRAN4_SUPPORTED_MIN 0x0 > #define ID_AA64MMFR0_TGRAN4_SUPPORTED_MAX 0x7 > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c > index f8a3067d10c6..2f5042bb107c 100644 > --- a/arch/arm64/kernel/cpufeature.c > +++ b/arch/arm64/kernel/cpufeature.c > @@ -2328,6 +2328,16 @@ static const struct arm64_cpu_capabilities arm64_features[] = { > .matches = has_cpuid_feature, > .min_field_value = 1, > }, > + { > + .desc = "Enhanced Counter Virtualization (Physical)", > + .capability = ARM64_HAS_ECV2, > + .type = ARM64_CPUCAP_SYSTEM_FEATURE, > + .sys_reg = SYS_ID_AA64MMFR0_EL1, > + .sign = FTR_UNSIGNED, > + .field_pos = ID_AA64MMFR0_ECV_SHIFT, > + .matches = has_cpuid_feature, > + .min_field_value = ID_AA64MMFR0_ECV_PHYS, > + }, > {}, > }; > > diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps > index 49305c2e6dfd..f73a30d5fb1c 100644 > --- a/arch/arm64/tools/cpucaps > +++ b/arch/arm64/tools/cpucaps > @@ -18,6 +18,7 @@ HAS_CRC32 > HAS_DCPODP > HAS_DCPOP > HAS_E0PD > +HAS_ECV2 > HAS_EPAN > HAS_GENERIC_AUTH > HAS_GENERIC_AUTH_ARCH > -- Reviewed-by: Reiji Watanabe <reijiw@google.com> Personally, I would prefer a more descriptive name (e.g. ECV_PHYS) rather than ECV2 though. Thanks, Reiji
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index b268082d67ed..3fa6b091384d 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -849,6 +849,7 @@ #define ID_AA64MMFR0_ASID_8 0x0 #define ID_AA64MMFR0_ASID_16 0x2 +#define ID_AA64MMFR0_ECV_PHYS 0x2 #define ID_AA64MMFR0_TGRAN4_NI 0xf #define ID_AA64MMFR0_TGRAN4_SUPPORTED_MIN 0x0 #define ID_AA64MMFR0_TGRAN4_SUPPORTED_MAX 0x7 diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index f8a3067d10c6..2f5042bb107c 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -2328,6 +2328,16 @@ static const struct arm64_cpu_capabilities arm64_features[] = { .matches = has_cpuid_feature, .min_field_value = 1, }, + { + .desc = "Enhanced Counter Virtualization (Physical)", + .capability = ARM64_HAS_ECV2, + .type = ARM64_CPUCAP_SYSTEM_FEATURE, + .sys_reg = SYS_ID_AA64MMFR0_EL1, + .sign = FTR_UNSIGNED, + .field_pos = ID_AA64MMFR0_ECV_SHIFT, + .matches = has_cpuid_feature, + .min_field_value = ID_AA64MMFR0_ECV_PHYS, + }, {}, }; diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps index 49305c2e6dfd..f73a30d5fb1c 100644 --- a/arch/arm64/tools/cpucaps +++ b/arch/arm64/tools/cpucaps @@ -18,6 +18,7 @@ HAS_CRC32 HAS_DCPODP HAS_DCPOP HAS_E0PD +HAS_ECV2 HAS_EPAN HAS_GENERIC_AUTH HAS_GENERIC_AUTH_ARCH
Introduce a new cpucap to indicate if the system supports full enhanced counter virtualization (i.e. ID_AA64MMFR0_EL1.ECV>=0x2). Signed-off-by: Oliver Upton <oupton@google.com> --- arch/arm64/include/asm/sysreg.h | 1 + arch/arm64/kernel/cpufeature.c | 10 ++++++++++ arch/arm64/tools/cpucaps | 1 + 3 files changed, 12 insertions(+)