| Message ID | 20210921155218.10387-10-jason-jh.lin@mediatek.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add Mediatek Soc DRM (vdosys0) support for mt8195 | expand |
> Add mt8195 vdosys0 clock driver name and routing table to > the driver data of mtk-mmsys. > > Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com> > --- > This patch is base on [1] > [1] soc: mediatek: mmsys: add mt8192 mmsys support > - https://patchwork.kernel.org/project/linux-mediatek/list/?series=524857 > > The vdosys1 impelmentation patch [2] > [2] soc: mediatek: add mtk-mmsys support for mt8195 vdosys1 > - https://patchwork.kernel.org/project/linux-mediatek/patch/20210906071539.12953-7-nancy.lin@mediatek.com/ > --- Hello Jason, thanks for the patch! However, there are a few things to improve: > drivers/soc/mediatek/mt8195-mmsys.h | 114 +++++++++++++++++++++++++ > drivers/soc/mediatek/mtk-mmsys.c | 11 +++ > include/linux/soc/mediatek/mtk-mmsys.h | 9 ++ > 3 files changed, 134 insertions(+) > create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h > > diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h > new file mode 100644 > index 000000000000..0c97a5f016c1 > --- /dev/null > +++ b/drivers/soc/mediatek/mt8195-mmsys.h > @@ -0,0 +1,114 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ > + > +#ifndef __SOC_MEDIATEK_MT8195_MMSYS_H > +#define __SOC_MEDIATEK_MT8195_MMSYS_H > + > +#define MT8195_VDO0_OVL_MOUT_EN 0xf14 > +#define MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0 BIT(0) > +#define MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0 BIT(1) > +#define MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1 BIT(2) > +#define MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1 BIT(4) > +#define MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1 BIT(5) > +#define MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0 BIT(6) > + > +#define MT8195_VDO0_SEL_IN 0xf34 > +#define MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT (0 << 0) Bitshifting 0 by 0 bits == 0, so this is simply 0. > +#define MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1 (1 << 0) I would write 0x1 here > +#define MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0 (2 << 0) ....and 0x2 here: bitshifting of 0 bits makes little sense. > +#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0 (0 << 4) Bitshifting 0 by 4 bits is still 0, so this is again 0. This is repeated too many times, so I will not list it for all of the occurrences. > +#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE (1 << 4) This is BIT(4). > +#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1 (0 << 5) > +#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE (1 << 5) ...and this is BIT(5) > +#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE (0 << 8) > +#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT (1 << 8) BIT(8) > +#define MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT (0 << 9) > +#define MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT (0 << 12) > +#define MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE (1 << 12) BIT(12) > +#define MT8195_SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0 (2 << 12) BIT(13) ... and please, use the BIT(nr) macro for all these bit definitions, it's way more readable like that. Regards, - Angelo
Hi Angelo, Thanks for the reviews. On Thu, 2021-10-14 at 16:05 +0200, AngeloGioacchino Del Regno wrote: > > Add mt8195 vdosys0 clock driver name and routing table to > > the driver data of mtk-mmsys. > > [snip] > > > > --- > > Hello Jason, > thanks for the patch! However, there are a few things to improve: > [snip] > > +#define MT8195_VDO0_SEL_IN 0xf34 > > +#define MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT (0 << > > 0) > > Bitshifting 0 by 0 bits == 0, so this is simply 0. > > > +#define MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1 (1 << > > 0) > > I would write 0x1 here > > > +#define MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0 (2 << > > 0) > > ....and 0x2 here: bitshifting of 0 bits makes little sense. > > > +#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0 > > (0 << 4) > > Bitshifting 0 by 4 bits is still 0, so this is again 0. > This is repeated too many times, so I will not list it for all of the > occurrences. > > > +#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE (1 << > > 4) > > This is BIT(4). > > > +#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1 > > (0 << 5) > +#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE > > (1 << 5) > > ...and this is BIT(5) > > > +#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE (0 << > > 8) > > +#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT > > (1 << 8) > > BIT(8) > > > +#define MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT > > (0 << 9) > > +#define MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT (0 << > > 12) > > +#define MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE > > (1 << 12) > > BIT(12) > > > +#define MT8195_SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0 (2 << > > 12) > > BIT(13) > > ... and please, use the BIT(nr) macro for all these bit definitions, > it's way more > readable like that. > > Regards, > - Angelo Because the HW register design of MT8195_VDO0_SEL_IN 0xf34 is like this: bit[1:0] as MT8195_SEL_IN_VPP_MERGE and value: 0 as MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT value: 1 as MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1 value: 2 as MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0 bit[4:4] as MT8195_SEL_IN_DSC_WRAP0_IN and value 0 as MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0 value 1 as MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE bit[5:5] as MT8195_SEL_IN_DSC_WRAP1_IN and value 0 as MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1 value 1 as MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE and so on... I think using BIT(nr) macro directly is not easy to debug. Is it better to define another MACRO like this? #define BIT_VAL(val, bit) ((val) << (bit)) #define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0 BIT_VAL(0, 4) #define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE BIT_VAL(1, 4) ... or #define MT8195_SEL_IN_DSC_WRAP0_IN (4) #define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0 (0 << MT8195_SEL_IN_DSC_WRAP0_IN) #define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE (1 << MT8195_SEL_IN_DSC_WRAP0_IN) ... What do you think? Regards, Jason-JH Lin <jason-jh.lin@mediatek.com>
On Fri, Oct 22, 2021 at 6:13 PM Jason-JH Lin <jason-jh.lin@mediatek.com> wrote: > > Hi Angelo, > > Thanks for the reviews. > > > On Thu, 2021-10-14 at 16:05 +0200, AngeloGioacchino Del Regno wrote: > > > Add mt8195 vdosys0 clock driver name and routing table to > > > the driver data of mtk-mmsys. > > > > > [snip] > > > > > > > --- > > > > Hello Jason, > > thanks for the patch! However, there are a few things to improve: > > > > [snip] > > > > +#define MT8195_VDO0_SEL_IN 0xf34 > > > +#define MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT (0 << > > > 0) > > > > Bitshifting 0 by 0 bits == 0, so this is simply 0. > > > > > +#define MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1 (1 << > > > 0) > > > > I would write 0x1 here > > > > > +#define MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0 (2 << > > > 0) > > > > ....and 0x2 here: bitshifting of 0 bits makes little sense. > > > > > +#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0 > > > (0 << 4) > > > > Bitshifting 0 by 4 bits is still 0, so this is again 0. > > This is repeated too many times, so I will not list it for all of the > > occurrences. > > > > > +#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE (1 << > > > 4) > > > > This is BIT(4). > > > > > +#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1 > > > (0 << 5) > +#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE > > > (1 << 5) > > > > ...and this is BIT(5) > > > > > +#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE (0 << > > > 8) > > > +#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT > > > (1 << 8) > > > > BIT(8) > > > > > +#define MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT > > > (0 << 9) > > > +#define MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT (0 << > > > 12) > > > +#define MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE > > > (1 << 12) > > > > BIT(12) > > > > > +#define MT8195_SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0 (2 << > > > 12) > > > > BIT(13) > > > > ... and please, use the BIT(nr) macro for all these bit definitions, > > it's way more > > readable like that. > > > > Regards, > > - Angelo > > Because the HW register design of MT8195_VDO0_SEL_IN 0xf34 is like > this: > > bit[1:0] as MT8195_SEL_IN_VPP_MERGE and > value: 0 as MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT > value: 1 as MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1 > value: 2 as MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0 > bit[4:4] as MT8195_SEL_IN_DSC_WRAP0_IN and > value 0 as MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0 > value 1 as MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE > bit[5:5] as MT8195_SEL_IN_DSC_WRAP1_IN and > value 0 as > MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1 > value 1 as > MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE > and so on... > > I think using BIT(nr) macro directly is not easy to debug. > > > Is it better to define another MACRO like this? > > #define BIT_VAL(val, bit) ((val) << (bit)) > #define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0 BIT_VAL(0, 4) > #define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE BIT_VAL(1, 4) > ... > > or > > #define MT8195_SEL_IN_DSC_WRAP0_IN (4) > #define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0 (0 > << MT8195_SEL_IN_DSC_WRAP0_IN) > #define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE (1 << > MT8195_SEL_IN_DSC_WRAP0_IN) > ... > > What do you think? Hi Jason, If that's the case you can still use BIT(nr) for the definitions and describe their usage in the comment, so both code readability and the ease of maintenance are preserved, and people can easily tell if there are duplicated/missing definitions while reading through the code. Adding informative comments is never a bad thing. I would do something like this (and further split the definitions into sections by their functionalities with blank lines for visual comfort): /* * MT8195_VDO0_SEL_IN[1:0]: VPP_MERGE * 0x0 : DSC_WRAP0_OUT * 0x1 : DISP_DITHER1 * 0x10: VDO1_VIRTUAL0 */ #define MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT 0 #define MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1 BIT(0) #define MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0 BIT(1) /* * MT8195_VDO0_SEL_IN[4:4]: DSC_WRAP0_IN * 0x0: DISP_DITHER0 * 0x1: VPP_MERGE */ #define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0 0 #define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE BIT(4) ... and so on. Regards, Fei > > > Regards, > Jason-JH Lin <jason-jh.lin@mediatek.com> >
Hi Fei, Thanks for the reviews. On Mon, 2021-10-25 at 13:05 +0800, Fei Shao wrote: > On Fri, Oct 22, 2021 at 6:13 PM Jason-JH Lin < > jason-jh.lin@mediatek.com> wrote: > > > > Hi Angelo, > > > > Thanks for the reviews. > > > > > > On Thu, 2021-10-14 at 16:05 +0200, AngeloGioacchino Del Regno > > wrote: > > > > Add mt8195 vdosys0 clock driver name and routing table to > > > > the driver data of mtk-mmsys. > > > > > > > > [snip] > > > > > > > > > > --- > > > > > > Hello Jason, > > > thanks for the patch! However, there are a few things to improve: > > > > > > > [snip] > > > > > > +#define > > > > MT8195_VDO0_SEL_IN 0xf34 > > > > +#define MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT (0 > > > > << > > > > 0) > > > > > > Bitshifting 0 by 0 bits == 0, so this is simply 0. > > > > > > > +#define MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1 (1 > > > > << > > > > 0) > > > > > > I would write 0x1 here > > > > > > > +#define MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0 (2 > > > > << > > > > 0) > > > > > > ....and 0x2 here: bitshifting of 0 bits makes little sense. > > > > > > > +#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0 > > > > (0 << 4) > > > > > > Bitshifting 0 by 4 bits is still 0, so this is again 0. > > > This is repeated too many times, so I will not list it for all of > > > the > > > occurrences. > > > > > > > +#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE (1 > > > > << > > > > 4) > > > > > > This is BIT(4). > > > > > > > +#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1 > > > > (0 << 5) > +#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE > > > > (1 << 5) > > > > > > ...and this is BIT(5) > > > > > > > +#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE (0 > > > > << > > > > 8) > > > > +#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT > > > > (1 << 8) > > > > > > BIT(8) > > > > > > > +#define MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT > > > > (0 << 9) > > > > +#define MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT (0 > > > > << > > > > 12) > > > > +#define MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE > > > > (1 << 12) > > > > > > BIT(12) > > > > > > > +#define MT8195_SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0 (2 > > > > << > > > > 12) > > > > > > BIT(13) > > > > > > ... and please, use the BIT(nr) macro for all these bit > > > definitions, > > > it's way more > > > readable like that. > > > > > > Regards, > > > - Angelo > > > > Because the HW register design of MT8195_VDO0_SEL_IN 0xf34 is like > > this: > > > > bit[1:0] as MT8195_SEL_IN_VPP_MERGE and > > value: 0 as MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT > > value: 1 as MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1 > > value: 2 as MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0 > > bit[4:4] as MT8195_SEL_IN_DSC_WRAP0_IN and > > value 0 as MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0 > > value 1 as MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE > > bit[5:5] as MT8195_SEL_IN_DSC_WRAP1_IN and > > value 0 as > > MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1 > > value 1 as > > MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE > > and so on... > > > > I think using BIT(nr) macro directly is not easy to debug. > > > > > > Is it better to define another MACRO like this? > > > > #define BIT_VAL(val, bit) ((val) << (bit)) > > #define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0 BIT_VAL(0, 4) > > #define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE BIT_VAL(1, 4) > > ... > > > > or > > > > #define MT8195_SEL_IN_DSC_WRAP0_IN (4) > > #define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0 (0 > > << MT8195_SEL_IN_DSC_WRAP0_IN) > > #define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE (1 << > > MT8195_SEL_IN_DSC_WRAP0_IN) > > ... > > > > What do you think? > > Hi Jason, > > If that's the case you can still use BIT(nr) for the definitions and > describe their usage in the comment, so both code readability and the > ease of maintenance are preserved, and people can easily tell if > there > are duplicated/missing definitions while reading through the code. > Adding informative comments is never a bad thing. > > I would do something like this (and further split the definitions > into > sections by their functionalities with blank lines for visual > comfort): > > /* > * MT8195_VDO0_SEL_IN[1:0]: VPP_MERGE > * 0x0 : DSC_WRAP0_OUT > * 0x1 : DISP_DITHER1 > * 0x10: VDO1_VIRTUAL0 > */ > #define MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT 0 > #define MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1 BIT(0) > #define MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0 BIT(1) > > /* > * MT8195_VDO0_SEL_IN[4:4]: DSC_WRAP0_IN > * 0x0: DISP_DITHER0 > * 0x1: VPP_MERGE > */ > #define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0 0 > #define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE BIT(4) > ... and so on. > > Regards, > Fei > OK, I'll fix it. > > > > > > Regards, > > Jason-JH Lin <jason-jh.lin@mediatek.com> > >
diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h new file mode 100644 index 000000000000..0c97a5f016c1 --- /dev/null +++ b/drivers/soc/mediatek/mt8195-mmsys.h @@ -0,0 +1,114 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_MEDIATEK_MT8195_MMSYS_H +#define __SOC_MEDIATEK_MT8195_MMSYS_H + +#define MT8195_VDO0_OVL_MOUT_EN 0xf14 +#define MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0 BIT(0) +#define MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0 BIT(1) +#define MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1 BIT(2) +#define MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1 BIT(4) +#define MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1 BIT(5) +#define MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0 BIT(6) + +#define MT8195_VDO0_SEL_IN 0xf34 +#define MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT (0 << 0) +#define MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1 (1 << 0) +#define MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0 (2 << 0) +#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0 (0 << 4) +#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE (1 << 4) +#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1 (0 << 5) +#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE (1 << 5) +#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE (0 << 8) +#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT (1 << 8) +#define MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT (0 << 9) +#define MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT (0 << 12) +#define MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE (1 << 12) +#define MT8195_SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0 (2 << 12) +#define MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT (0 << 16) +#define MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0 (1 << 16) +#define MT8195_SEL_IN_DSI1_FROM_DSC_WRAP1_OUT (0 << 17) +#define MT8195_SEL_IN_DSI1_FROM_VPP_MERGE (1 << 17) +#define MT8195_SEL_IN_DISP_WDMA1_FROM_DISP_OVL1 (0 << 20) +#define MT8195_SEL_IN_DISP_WDMA1_FROM_VPP_MERGE (1 << 20) +#define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN (0 << 21) +#define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1 (1 << 21) +#define MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0 (0 << 22) +#define MT8195_SEL_IN_DISP_WDMA0_FROM_VPP_MERGE (1 << 22) + +#define MT8195_VDO0_SEL_OUT 0xf38 +#define MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN (0 << 0) +#define MT8195_SOUT_DISP_DITHER0_TO_DSI0 (1 << 0) +#define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN (0 << 1) +#define MT8195_SOUT_DISP_DITHER1_TO_VPP_MERGE (1 << 1) +#define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT (2 << 1) +#define MT8195_SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE (0 << 4) +#define MT8195_SOUT_VDO1_VIRTUAL0_TO_DP_INTF0 (1 << 4) +#define MT8195_SOUT_VPP_MERGE_TO_DSI1 (0 << 8) +#define MT8195_SOUT_VPP_MERGE_TO_DP_INTF0 (1 << 8) +#define MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0 (2 << 8) +#define MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA1 (3 << 8) +#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN (4 << 8) +#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN (0 << 11) +#define MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA0 (1 << 11) +#define MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0 (0 << 12) +#define MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0 (1 << 12) +#define MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE (2 << 12) +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_DSI1 (0 << 16) +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_DP_INTF0 (1 << 16) +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0 (2 << 16) +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE (3 << 16) + +static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = { + { + DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0, + MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0, + MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0 + }, { + DDP_COMPONENT_OVL1, DDP_COMPONENT_RDMA1, + MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1, + MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1 + }, { + DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT, + MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT + }, { + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF0, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE, + MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE + }, { + DDP_COMPONENT_DITHER, DDP_COMPONENT_DSC0, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0, + MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0 + }, { + DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT, + MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT + }, { + DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0, + MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0 + }, { + DDP_COMPONENT_DITHER, DDP_COMPONENT_DSC0, + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN, + MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN + }, { + DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0, + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_DSI0, + MT8195_SOUT_DISP_DITHER0_TO_DSI0 + }, { + DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0, + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0, + MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0 + }, { + DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0, + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE, + MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE + }, { + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF0, + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_DP_INTF0, + MT8195_SOUT_VPP_MERGE_TO_DP_INTF0 + } +}; + +#endif /* __SOC_MEDIATEK_MT8195_MMSYS_H */ diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c index 63fccdf3d491..8f5650f723ad 100644 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ b/drivers/soc/mediatek/mtk-mmsys.c @@ -15,6 +15,7 @@ #include "mt8183-mmsys.h" #include "mt8365-mmsys.h" #include "mt8192-mmsys.h" +#include "mt8195-mmsys.h" static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { .clk_driver = "clk-mt2701-mm", @@ -60,6 +61,12 @@ static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = { .num_routes = ARRAY_SIZE(mmsys_mt8192_routing_table), }; +static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = { + .clk_driver = "clk-mt8195-vdo0", + .routes = mmsys_mt8195_routing_table, + .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table), +}; + static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = { .clk_driver = "clk-mt8365-mm", .routes = mt8365_mmsys_routing_table, @@ -178,6 +185,10 @@ static const struct of_device_id of_match_mtk_mmsys[] = { .compatible = "mediatek,mt8192-mmsys", .data = &mt8192_mmsys_driver_data, }, + { + .compatible = "mediatek,mt8195-vdosys0", + .data = &mt8195_vdosys0_driver_data, + }, { .compatible = "mediatek,mt8365-mmsys", .data = &mt8365_mmsys_driver_data, diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h index 4bba275e235a..64c77c4a6c56 100644 --- a/include/linux/soc/mediatek/mtk-mmsys.h +++ b/include/linux/soc/mediatek/mtk-mmsys.h @@ -17,13 +17,22 @@ enum mtk_ddp_comp_id { DDP_COMPONENT_COLOR0, DDP_COMPONENT_COLOR1, DDP_COMPONENT_DITHER, + DDP_COMPONENT_DP_INTF0, DDP_COMPONENT_DPI0, DDP_COMPONENT_DPI1, + DDP_COMPONENT_DSC0, + DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI0, DDP_COMPONENT_DSI1, DDP_COMPONENT_DSI2, DDP_COMPONENT_DSI3, DDP_COMPONENT_GAMMA, + DDP_COMPONENT_MERGE0, + DDP_COMPONENT_MERGE1, + DDP_COMPONENT_MERGE2, + DDP_COMPONENT_MERGE3, + DDP_COMPONENT_MERGE4, + DDP_COMPONENT_MERGE5, DDP_COMPONENT_OD0, DDP_COMPONENT_OD1, DDP_COMPONENT_OVL0,
Add mt8195 vdosys0 clock driver name and routing table to the driver data of mtk-mmsys. Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com> --- This patch is base on [1] [1] soc: mediatek: mmsys: add mt8192 mmsys support - https://patchwork.kernel.org/project/linux-mediatek/list/?series=524857 The vdosys1 impelmentation patch [2] [2] soc: mediatek: add mtk-mmsys support for mt8195 vdosys1 - https://patchwork.kernel.org/project/linux-mediatek/patch/20210906071539.12953-7-nancy.lin@mediatek.com/ --- drivers/soc/mediatek/mt8195-mmsys.h | 114 +++++++++++++++++++++++++ drivers/soc/mediatek/mtk-mmsys.c | 11 +++ include/linux/soc/mediatek/mtk-mmsys.h | 9 ++ 3 files changed, 134 insertions(+) create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h