diff mbox series

[v2,3/5] dt-bindings: clock: Add bindings definitions for Exynos850 CMU

Message ID 20211007194113.10507-4-semen.protsenko@linaro.org (mailing list archive)
State New, archived
Headers show
Series clk: samsung: Introduce Exynos850 SoC clock driver | expand

Commit Message

Sam Protsenko Oct. 7, 2021, 7:41 p.m. UTC 
Clock controller driver is designed to have separate instances for each
particular CMU. So clock IDs in this bindings header also start from 1
for each CMU.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Acked-by: Rob Herring <robh@kernel.org>
---
Changes in v2:
  - Added all clock ids
  - Added CLK_ prefix for all clock constants
  - Added R-b tag by Krzysztof Kozlowski
  - Added Ack tag by Rob Herring

 include/dt-bindings/clock/exynos850.h | 141 ++++++++++++++++++++++++++
 1 file changed, 141 insertions(+)
 create mode 100644 include/dt-bindings/clock/exynos850.h

Comments

Krzysztof Kozlowski Oct. 8, 2021, 6:45 a.m. UTC | #1 
On 07/10/2021 21:41, Sam Protsenko wrote:
> Clock controller driver is designed to have separate instances for each
> particular CMU. So clock IDs in this bindings header also start from 1
> for each CMU.
> 
> Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
> Acked-by: Rob Herring <robh@kernel.org>
> ---
> Changes in v2:
>   - Added all clock ids
>   - Added CLK_ prefix for all clock constants
>   - Added R-b tag by Krzysztof Kozlowski
>   - Added Ack tag by Rob Herring
> 
>  include/dt-bindings/clock/exynos850.h | 141 ++++++++++++++++++++++++++
>  1 file changed, 141 insertions(+)
>  create mode 100644 include/dt-bindings/clock/exynos850.h
> 
> diff --git a/include/dt-bindings/clock/exynos850.h b/include/dt-bindings/clock/exynos850.h
> new file mode 100644
> index 000000000000..a44c5f91d3c7
> --- /dev/null
> +++ b/include/dt-bindings/clock/exynos850.h
> @@ -0,0 +1,141 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */

The bindings are preferred to be under GPL-2.0+BSD. I don't know about
such policy for the headers but it seems reasonable - allows re-usage in
other systems. Do you mind licensing it under:
GPL-2.0-only or BSD-2-Clause
?

Best regards,
Krzysztof

> +/*
> + * Copyright (C) 2021 Linaro Ltd.
> + * Author: Sam Protsenko <semen.protsenko@linaro.org>
> + *
> + * Device Tree binding constants for Exynos850 clock controller.
> + */
> +
> +#ifndef _DT_BINDINGS_CLOCK_EXYNOS_850_H
> +#define _DT_BINDINGS_CLOCK_EXYNOS_850_H
> +
> +/* CMU_TOP */
Sam Protsenko Oct. 8, 2021, 3:31 p.m. UTC | #2 
On Fri, 8 Oct 2021 at 09:45, Krzysztof Kozlowski
<krzysztof.kozlowski@canonical.com> wrote:
>
> On 07/10/2021 21:41, Sam Protsenko wrote:
> > Clock controller driver is designed to have separate instances for each
> > particular CMU. So clock IDs in this bindings header also start from 1
> > for each CMU.
> >
> > Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
> > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
> > Acked-by: Rob Herring <robh@kernel.org>
> > ---
> > Changes in v2:
> >   - Added all clock ids
> >   - Added CLK_ prefix for all clock constants
> >   - Added R-b tag by Krzysztof Kozlowski
> >   - Added Ack tag by Rob Herring
> >
> >  include/dt-bindings/clock/exynos850.h | 141 ++++++++++++++++++++++++++
> >  1 file changed, 141 insertions(+)
> >  create mode 100644 include/dt-bindings/clock/exynos850.h
> >
> > diff --git a/include/dt-bindings/clock/exynos850.h b/include/dt-bindings/clock/exynos850.h
> > new file mode 100644
> > index 000000000000..a44c5f91d3c7
> > --- /dev/null
> > +++ b/include/dt-bindings/clock/exynos850.h
> > @@ -0,0 +1,141 @@
> > +/* SPDX-License-Identifier: GPL-2.0-only */
>
> The bindings are preferred to be under GPL-2.0+BSD. I don't know about
> such policy for the headers but it seems reasonable - allows re-usage in
> other systems. Do you mind licensing it under:
> GPL-2.0-only or BSD-2-Clause
> ?
>

Sure, will do in v3.

> Best regards,
> Krzysztof
>
> > +/*
> > + * Copyright (C) 2021 Linaro Ltd.
> > + * Author: Sam Protsenko <semen.protsenko@linaro.org>
> > + *
> > + * Device Tree binding constants for Exynos850 clock controller.
> > + */
> > +
> > +#ifndef _DT_BINDINGS_CLOCK_EXYNOS_850_H
> > +#define _DT_BINDINGS_CLOCK_EXYNOS_850_H
> > +
> > +/* CMU_TOP */
Chanwoo Choi Oct. 15, 2021, 12:47 a.m. UTC | #3 
On 10/8/21 4:41 AM, Sam Protsenko wrote:
> Clock controller driver is designed to have separate instances for each
> particular CMU. So clock IDs in this bindings header also start from 1
> for each CMU.
> 
> Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
> Acked-by: Rob Herring <robh@kernel.org>
> ---
> Changes in v2:
>   - Added all clock ids
>   - Added CLK_ prefix for all clock constants
>   - Added R-b tag by Krzysztof Kozlowski
>   - Added Ack tag by Rob Herring
> 
>  include/dt-bindings/clock/exynos850.h | 141 ++++++++++++++++++++++++++
>  1 file changed, 141 insertions(+)
>  create mode 100644 include/dt-bindings/clock/exynos850.h
> 
> diff --git a/include/dt-bindings/clock/exynos850.h b/include/dt-bindings/clock/exynos850.h
> new file mode 100644
> index 000000000000..a44c5f91d3c7
> --- /dev/null
> +++ b/include/dt-bindings/clock/exynos850.h
> @@ -0,0 +1,141 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (C) 2021 Linaro Ltd.
> + * Author: Sam Protsenko <semen.protsenko@linaro.org>
> + *
> + * Device Tree binding constants for Exynos850 clock controller.
> + */
> +
> +#ifndef _DT_BINDINGS_CLOCK_EXYNOS_850_H
> +#define _DT_BINDINGS_CLOCK_EXYNOS_850_H
> +
> +/* CMU_TOP */
> +#define CLK_FOUT_SHARED0_PLL		1
> +#define CLK_FOUT_SHARED1_PLL		2
> +#define CLK_FOUT_MMC_PLL		3
> +#define CLK_MOUT_SHARED0_PLL		4
> +#define CLK_MOUT_SHARED1_PLL		5
> +#define CLK_MOUT_MMC_PLL		6
> +#define CLK_MOUT_CORE_BUS		7
> +#define CLK_MOUT_CORE_CCI		8
> +#define CLK_MOUT_CORE_MMC_EMBD		9
> +#define CLK_MOUT_CORE_SSS		10
> +#define CLK_MOUT_DPU			11
> +#define CLK_MOUT_HSI_BUS		12
> +#define CLK_MOUT_HSI_MMC_CARD		13
> +#define CLK_MOUT_HSI_USB20DRD		14
> +#define CLK_MOUT_PERI_BUS		15
> +#define CLK_MOUT_PERI_UART		16
> +#define CLK_MOUT_PERI_IP		17
> +#define CLK_DOUT_SHARED0_DIV3		18
> +#define CLK_DOUT_SHARED0_DIV2		19
> +#define CLK_DOUT_SHARED1_DIV3		20
> +#define CLK_DOUT_SHARED1_DIV2		21
> +#define CLK_DOUT_SHARED0_DIV4		22
> +#define CLK_DOUT_SHARED1_DIV4		23
> +#define CLK_DOUT_CORE_BUS		24
> +#define CLK_DOUT_CORE_CCI		25
> +#define CLK_DOUT_CORE_MMC_EMBD		26
> +#define CLK_DOUT_CORE_SSS		27
> +#define CLK_DOUT_DPU			28
> +#define CLK_DOUT_HSI_BUS		29
> +#define CLK_DOUT_HSI_MMC_CARD		30
> +#define CLK_DOUT_HSI_USB20DRD		31
> +#define CLK_DOUT_PERI_BUS		32
> +#define CLK_DOUT_PERI_UART		33
> +#define CLK_DOUT_PERI_IP		34
> +#define CLK_GOUT_CORE_BUS		35
> +#define CLK_GOUT_CORE_CCI		36
> +#define CLK_GOUT_CORE_MMC_EMBD		37
> +#define CLK_GOUT_CORE_SSS		38
> +#define CLK_GOUT_DPU			39
> +#define CLK_GOUT_HSI_BUS		40
> +#define CLK_GOUT_HSI_MMC_CARD		41
> +#define CLK_GOUT_HSI_USB20DRD		42
> +#define CLK_GOUT_PERI_BUS		43
> +#define CLK_GOUT_PERI_UART		44
> +#define CLK_GOUT_PERI_IP		45
> +#define TOP_NR_CLK			46
> +
> +/* CMU_HSI */
> +#define CLK_MOUT_HSI_BUS_USER		1
> +#define CLK_MOUT_HSI_MMC_CARD_USER	2
> +#define CLK_MOUT_HSI_USB20DRD_USER	3
> +#define CLK_MOUT_HSI_RTC		4
> +#define CLK_GOUT_USB_RTC_CLK		5
> +#define CLK_GOUT_USB_REF_CLK		6
> +#define CLK_GOUT_USB_PHY_REF_CLK	7
> +#define CLK_GOUT_USB_PHY_ACLK		8
> +#define CLK_GOUT_USB_BUS_EARLY_CLK	9
> +#define CLK_GOUT_GPIO_HSI_PCLK		10
> +#define CLK_GOUT_MMC_CARD_ACLK		11
> +#define CLK_GOUT_MMC_CARD_SDCLKIN	12
> +#define CLK_GOUT_SYSREG_HSI_PCLK	13
> +#define HSI_NR_CLK			14
> +
> +/* CMU_PERI */
> +#define CLK_MOUT_PERI_BUS_USER		1
> +#define CLK_MOUT_PERI_UART_USER		2
> +#define CLK_MOUT_PERI_HSI2C_USER	3
> +#define CLK_MOUT_PERI_SPI_USER		4
> +#define CLK_DOUT_PERI_HSI2C0		5
> +#define CLK_DOUT_PERI_HSI2C1		6
> +#define CLK_DOUT_PERI_HSI2C2		7
> +#define CLK_DOUT_PERI_SPI0		8
> +#define CLK_GOUT_PERI_HSI2C0		9
> +#define CLK_GOUT_PERI_HSI2C1		10
> +#define CLK_GOUT_PERI_HSI2C2		11
> +#define CLK_GOUT_GPIO_PERI_PCLK		12
> +#define CLK_GOUT_HSI2C0_IPCLK		13
> +#define CLK_GOUT_HSI2C0_PCLK		14
> +#define CLK_GOUT_HSI2C1_IPCLK		15
> +#define CLK_GOUT_HSI2C1_PCLK		16
> +#define CLK_GOUT_HSI2C2_IPCLK		17
> +#define CLK_GOUT_HSI2C2_PCLK		18
> +#define CLK_GOUT_I2C0_PCLK		19
> +#define CLK_GOUT_I2C1_PCLK		20
> +#define CLK_GOUT_I2C2_PCLK		21
> +#define CLK_GOUT_I2C3_PCLK		22
> +#define CLK_GOUT_I2C4_PCLK		23
> +#define CLK_GOUT_I2C5_PCLK		24
> +#define CLK_GOUT_I2C6_PCLK		25
> +#define CLK_GOUT_MCT_PCLK		26
> +#define CLK_GOUT_PWM_MOTOR_PCLK		27
> +#define CLK_GOUT_SPI0_IPCLK		28
> +#define CLK_GOUT_SPI0_PCLK		29
> +#define CLK_GOUT_SYSREG_PERI_PCLK	30
> +#define CLK_GOUT_UART_IPCLK		31
> +#define CLK_GOUT_UART_PCLK		32
> +#define CLK_GOUT_WDT0_PCLK		33
> +#define CLK_GOUT_WDT1_PCLK		34
> +#define PERI_NR_CLK			35
> +
> +/* CMU_CORE */
> +#define CLK_MOUT_CORE_BUS_USER		1
> +#define CLK_MOUT_CORE_CCI_USER		2
> +#define CLK_MOUT_CORE_MMC_EMBD_USER	3
> +#define CLK_MOUT_CORE_SSS_USER		4
> +#define CLK_MOUT_CORE_GIC		5
> +#define CLK_DOUT_CORE_BUSP		6
> +#define CLK_GOUT_CCI_ACLK		7
> +#define CLK_GOUT_GIC_CLK		8
> +#define CLK_GOUT_MMC_EMBD_ACLK		9
> +#define CLK_GOUT_MMC_EMBD_SDCLKIN	10
> +#define CLK_GOUT_SSS_ACLK		11
> +#define CLK_GOUT_SSS_PCLK		12
> +#define CORE_NR_CLK			13
> +
> +/* CMU_DPU */
> +#define CLK_MOUT_DPU_USER		1
> +#define CLK_DOUT_DPU_BUSP		2
> +#define CLK_GOUT_DPU_CMU_DPU_PCLK	3
> +#define CLK_GOUT_DPU_DECON0_ACLK	4
> +#define CLK_GOUT_DPU_DMA_ACLK		5
> +#define CLK_GOUT_DPU_DPP_ACLK		6
> +#define CLK_GOUT_DPU_PPMU_ACLK		7
> +#define CLK_GOUT_DPU_PPMU_PCLK		8
> +#define CLK_GOUT_DPU_SMMU_CLK		9
> +#define CLK_GOUT_DPU_SYSREG_PCLK	10
> +#define DPU_NR_CLK			11
> +
> +#endif /* _DT_BINDINGS_CLOCK_EXYNOS_850_H */
> 

Acked-by: Chanwoo Choi <cw00.choi@samsung.com>

Thanks for your work.
diff mbox series

Patch

diff --git a/include/dt-bindings/clock/exynos850.h b/include/dt-bindings/clock/exynos850.h
new file mode 100644
index 000000000000..a44c5f91d3c7
--- /dev/null
+++ b/include/dt-bindings/clock/exynos850.h
@@ -0,0 +1,141 @@ 
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2021 Linaro Ltd.
+ * Author: Sam Protsenko <semen.protsenko@linaro.org>
+ *
+ * Device Tree binding constants for Exynos850 clock controller.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_EXYNOS_850_H
+#define _DT_BINDINGS_CLOCK_EXYNOS_850_H
+
+/* CMU_TOP */
+#define CLK_FOUT_SHARED0_PLL		1
+#define CLK_FOUT_SHARED1_PLL		2
+#define CLK_FOUT_MMC_PLL		3
+#define CLK_MOUT_SHARED0_PLL		4
+#define CLK_MOUT_SHARED1_PLL		5
+#define CLK_MOUT_MMC_PLL		6
+#define CLK_MOUT_CORE_BUS		7
+#define CLK_MOUT_CORE_CCI		8
+#define CLK_MOUT_CORE_MMC_EMBD		9
+#define CLK_MOUT_CORE_SSS		10
+#define CLK_MOUT_DPU			11
+#define CLK_MOUT_HSI_BUS		12
+#define CLK_MOUT_HSI_MMC_CARD		13
+#define CLK_MOUT_HSI_USB20DRD		14
+#define CLK_MOUT_PERI_BUS		15
+#define CLK_MOUT_PERI_UART		16
+#define CLK_MOUT_PERI_IP		17
+#define CLK_DOUT_SHARED0_DIV3		18
+#define CLK_DOUT_SHARED0_DIV2		19
+#define CLK_DOUT_SHARED1_DIV3		20
+#define CLK_DOUT_SHARED1_DIV2		21
+#define CLK_DOUT_SHARED0_DIV4		22
+#define CLK_DOUT_SHARED1_DIV4		23
+#define CLK_DOUT_CORE_BUS		24
+#define CLK_DOUT_CORE_CCI		25
+#define CLK_DOUT_CORE_MMC_EMBD		26
+#define CLK_DOUT_CORE_SSS		27
+#define CLK_DOUT_DPU			28
+#define CLK_DOUT_HSI_BUS		29
+#define CLK_DOUT_HSI_MMC_CARD		30
+#define CLK_DOUT_HSI_USB20DRD		31
+#define CLK_DOUT_PERI_BUS		32
+#define CLK_DOUT_PERI_UART		33
+#define CLK_DOUT_PERI_IP		34
+#define CLK_GOUT_CORE_BUS		35
+#define CLK_GOUT_CORE_CCI		36
+#define CLK_GOUT_CORE_MMC_EMBD		37
+#define CLK_GOUT_CORE_SSS		38
+#define CLK_GOUT_DPU			39
+#define CLK_GOUT_HSI_BUS		40
+#define CLK_GOUT_HSI_MMC_CARD		41
+#define CLK_GOUT_HSI_USB20DRD		42
+#define CLK_GOUT_PERI_BUS		43
+#define CLK_GOUT_PERI_UART		44
+#define CLK_GOUT_PERI_IP		45
+#define TOP_NR_CLK			46
+
+/* CMU_HSI */
+#define CLK_MOUT_HSI_BUS_USER		1
+#define CLK_MOUT_HSI_MMC_CARD_USER	2
+#define CLK_MOUT_HSI_USB20DRD_USER	3
+#define CLK_MOUT_HSI_RTC		4
+#define CLK_GOUT_USB_RTC_CLK		5
+#define CLK_GOUT_USB_REF_CLK		6
+#define CLK_GOUT_USB_PHY_REF_CLK	7
+#define CLK_GOUT_USB_PHY_ACLK		8
+#define CLK_GOUT_USB_BUS_EARLY_CLK	9
+#define CLK_GOUT_GPIO_HSI_PCLK		10
+#define CLK_GOUT_MMC_CARD_ACLK		11
+#define CLK_GOUT_MMC_CARD_SDCLKIN	12
+#define CLK_GOUT_SYSREG_HSI_PCLK	13
+#define HSI_NR_CLK			14
+
+/* CMU_PERI */
+#define CLK_MOUT_PERI_BUS_USER		1
+#define CLK_MOUT_PERI_UART_USER		2
+#define CLK_MOUT_PERI_HSI2C_USER	3
+#define CLK_MOUT_PERI_SPI_USER		4
+#define CLK_DOUT_PERI_HSI2C0		5
+#define CLK_DOUT_PERI_HSI2C1		6
+#define CLK_DOUT_PERI_HSI2C2		7
+#define CLK_DOUT_PERI_SPI0		8
+#define CLK_GOUT_PERI_HSI2C0		9
+#define CLK_GOUT_PERI_HSI2C1		10
+#define CLK_GOUT_PERI_HSI2C2		11
+#define CLK_GOUT_GPIO_PERI_PCLK		12
+#define CLK_GOUT_HSI2C0_IPCLK		13
+#define CLK_GOUT_HSI2C0_PCLK		14
+#define CLK_GOUT_HSI2C1_IPCLK		15
+#define CLK_GOUT_HSI2C1_PCLK		16
+#define CLK_GOUT_HSI2C2_IPCLK		17
+#define CLK_GOUT_HSI2C2_PCLK		18
+#define CLK_GOUT_I2C0_PCLK		19
+#define CLK_GOUT_I2C1_PCLK		20
+#define CLK_GOUT_I2C2_PCLK		21
+#define CLK_GOUT_I2C3_PCLK		22
+#define CLK_GOUT_I2C4_PCLK		23
+#define CLK_GOUT_I2C5_PCLK		24
+#define CLK_GOUT_I2C6_PCLK		25
+#define CLK_GOUT_MCT_PCLK		26
+#define CLK_GOUT_PWM_MOTOR_PCLK		27
+#define CLK_GOUT_SPI0_IPCLK		28
+#define CLK_GOUT_SPI0_PCLK		29
+#define CLK_GOUT_SYSREG_PERI_PCLK	30
+#define CLK_GOUT_UART_IPCLK		31
+#define CLK_GOUT_UART_PCLK		32
+#define CLK_GOUT_WDT0_PCLK		33
+#define CLK_GOUT_WDT1_PCLK		34
+#define PERI_NR_CLK			35
+
+/* CMU_CORE */
+#define CLK_MOUT_CORE_BUS_USER		1
+#define CLK_MOUT_CORE_CCI_USER		2
+#define CLK_MOUT_CORE_MMC_EMBD_USER	3
+#define CLK_MOUT_CORE_SSS_USER		4
+#define CLK_MOUT_CORE_GIC		5
+#define CLK_DOUT_CORE_BUSP		6
+#define CLK_GOUT_CCI_ACLK		7
+#define CLK_GOUT_GIC_CLK		8
+#define CLK_GOUT_MMC_EMBD_ACLK		9
+#define CLK_GOUT_MMC_EMBD_SDCLKIN	10
+#define CLK_GOUT_SSS_ACLK		11
+#define CLK_GOUT_SSS_PCLK		12
+#define CORE_NR_CLK			13
+
+/* CMU_DPU */
+#define CLK_MOUT_DPU_USER		1
+#define CLK_DOUT_DPU_BUSP		2
+#define CLK_GOUT_DPU_CMU_DPU_PCLK	3
+#define CLK_GOUT_DPU_DECON0_ACLK	4
+#define CLK_GOUT_DPU_DMA_ACLK		5
+#define CLK_GOUT_DPU_DPP_ACLK		6
+#define CLK_GOUT_DPU_PPMU_ACLK		7
+#define CLK_GOUT_DPU_PPMU_PCLK		8
+#define CLK_GOUT_DPU_SMMU_CLK		9
+#define CLK_GOUT_DPU_SYSREG_PCLK	10
+#define DPU_NR_CLK			11
+
+#endif /* _DT_BINDINGS_CLOCK_EXYNOS_850_H */