| Message ID | 20211104062144.31453-1-qizhong.cheng@mediatek.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | PCI: mediatek: Delay 100ms to wait power and clock to become stable | expand |
On Thursday 04 November 2021 14:21:44 qizhong cheng wrote: > Described in PCIe CEM specification setctions 2.2 (PERST# Signal) and > 2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should > be delayed 100ms (TPVPERL) for the power and clock to become stable. > > Signed-off-by: qizhong cheng <qizhong.cheng@mediatek.com> Acked-by: Pali Rohár <pali@kernel.org> > --- > drivers/pci/controller/pcie-mediatek.c | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/drivers/pci/controller/pcie-mediatek.c b/drivers/pci/controller/pcie-mediatek.c > index 2f3f974977a3..b32acbac8084 100644 > --- a/drivers/pci/controller/pcie-mediatek.c > +++ b/drivers/pci/controller/pcie-mediatek.c > @@ -702,6 +702,14 @@ static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port) > */ > writel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL); > > + /* > + * Described in PCIe CEM specification setctions 2.2 (PERST# Signal) > + * and 2.2.1 (Initial Power-Up (G3 to S0)). > + * The deassertion of PERST# should be delayed 100ms (TPVPERL) > + * for the power and clock to become stable. > + */ > + msleep(100); > + I guess that this change is fixing detection of some PCIe cards, right? This ad-hoc driver change is really required as kernel pci code does not contain this delay functionality. Note that this delay is required in every native pci controller driver (not only mediatek), otherwise some PCIe cards may not be detected. For future direction, some more general solution for these issues is needed. I proposed something in following email: https://lore.kernel.org/linux-pci/20211022183808.jdeo7vntnagqkg7g@pali/ If you have a time, I would like to hear some feedback... > /* De-assert PHY, PE, PIPE, MAC and configuration reset */ > val = readl(port->base + PCIE_RST_CTRL); > val |= PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB | > -- > 2.25.1 >
On Thu, 4 Nov 2021 14:21:44 +0800, qizhong cheng wrote: > Described in PCIe CEM specification setctions 2.2 (PERST# Signal) and > 2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should > be delayed 100ms (TPVPERL) for the power and clock to become stable. > > Applied to pci/mediatek, thanks! [1/1] PCI: mediatek: Delay 100ms to wait power and clock to become stable https://git.kernel.org/lpieralisi/pci/c/1fa610f217 Thanks, Lorenzo
On Thu, Nov 04, 2021 at 02:21:44PM +0800, qizhong cheng wrote: > Described in PCIe CEM specification setctions 2.2 (PERST# Signal) and > 2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should > be delayed 100ms (TPVPERL) for the power and clock to become stable. Thanks for the spec references. s/setctions/sections/ > Signed-off-by: qizhong cheng <qizhong.cheng@mediatek.com> > --- > drivers/pci/controller/pcie-mediatek.c | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/drivers/pci/controller/pcie-mediatek.c b/drivers/pci/controller/pcie-mediatek.c > index 2f3f974977a3..b32acbac8084 100644 > --- a/drivers/pci/controller/pcie-mediatek.c > +++ b/drivers/pci/controller/pcie-mediatek.c > @@ -702,6 +702,14 @@ static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port) > */ > writel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL); > > + /* > + * Described in PCIe CEM specification setctions 2.2 (PERST# Signal) > + * and 2.2.1 (Initial Power-Up (G3 to S0)). > + * The deassertion of PERST# should be delayed 100ms (TPVPERL) > + * for the power and clock to become stable. s/setctions/sections/ again. Otherwise we'll have a typo-fixing patch eventually. Please also rewrap into one paragraph. > + */ > + msleep(100); > + > /* De-assert PHY, PE, PIPE, MAC and configuration reset */ > val = readl(port->base + PCIE_RST_CTRL); > val |= PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB | > -- > 2.25.1 >
diff --git a/drivers/pci/controller/pcie-mediatek.c b/drivers/pci/controller/pcie-mediatek.c index 2f3f974977a3..b32acbac8084 100644 --- a/drivers/pci/controller/pcie-mediatek.c +++ b/drivers/pci/controller/pcie-mediatek.c @@ -702,6 +702,14 @@ static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port) */ writel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL); + /* + * Described in PCIe CEM specification setctions 2.2 (PERST# Signal) + * and 2.2.1 (Initial Power-Up (G3 to S0)). + * The deassertion of PERST# should be delayed 100ms (TPVPERL) + * for the power and clock to become stable. + */ + msleep(100); + /* De-assert PHY, PE, PIPE, MAC and configuration reset */ val = readl(port->base + PCIE_RST_CTRL); val |= PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB |
Described in PCIe CEM specification setctions 2.2 (PERST# Signal) and 2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should be delayed 100ms (TPVPERL) for the power and clock to become stable. Signed-off-by: qizhong cheng <qizhong.cheng@mediatek.com> --- drivers/pci/controller/pcie-mediatek.c | 8 ++++++++ 1 file changed, 8 insertions(+)