diff mbox series

[6/6] arm64: dts: mediatek: mt8195: add efuse node and cells

Message ID 20211107075646.4366-6-chunfeng.yun@mediatek.com (mailing list archive)
State New, archived
Headers show
Series [1/6] dt-bindings: nvmem: mediatek: add support bits property | expand

Commit Message

Chunfeng Yun Nov. 7, 2021, 7:56 a.m. UTC 
Add efuse node and cells used by t-phy to fix the bit shift issue

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
Depend on:

  [v4,1/1] arm64: dts: Add Mediatek SoC MT8195 and evaluation board dts and Makefile
  https://patchwork.kernel.org/patch/12509911
---
 arch/arm64/boot/dts/mediatek/mt8195.dtsi | 61 ++++++++++++++++++++++++
 1 file changed, 61 insertions(+)
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 263eebfd2ea1..7fb23c1cb8cc 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -933,6 +933,55 @@ 
 			status = "disabled";
 		};
 
+		efuse: efuse@11c10000 {
+			compatible = "mediatek,mt8195-efuse", "mediatek,efuse";
+			reg = <0 0x11c10000 0 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			status = "disabled";
+
+			u3_tx_imp_p0: usb3-tx-imp@184 {
+				reg = <0x184 0x1>;
+				bits = <0 5>;
+			};
+			u3_rx_imp_p0: usb3-rx-imp@184 {
+				reg = <0x184 0x2>;
+				bits = <5 5>;
+			};
+			u3_intr_p0: usb3-intr@185 {
+				reg = <0x185 0x1>;
+				bits = <2 6>;
+			};
+			comb_tx_imp_p1: usb3-tx-imp@186 {
+				reg = <0x186 0x1>;
+				bits = <0 5>;
+			};
+			comb_rx_imp_p1: usb3-rx-imp@186 {
+				reg = <0x186 0x2>;
+				bits = <5 5>;
+			};
+			comb_intr_p1: usb3-intr@187 {
+				reg = <0x187 0x1>;
+				bits = <2 6>;
+			};
+			u2_intr_p0: usb2-intr-p0@188 {
+				reg = <0x188 0x1>;
+				bits = <0 5>;
+			};
+			u2_intr_p1: usb2-intr-p1@188 {
+				reg = <0x188 0x2>;
+				bits = <5 5>;
+			};
+			u2_intr_p2: usb2-intr-p2@189 {
+				reg = <0x189 0x1>;
+				bits = <2 5>;
+			};
+			u2_intr_p3: usb2-intr-p3@189 {
+				reg = <0x189 0x2>;
+				bits = <7 5>;
+			};
+		};
+
 		u3phy2: t-phy@11c40000 {
 			compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v2";
 			#address-cells = <1>;
@@ -986,6 +1035,8 @@ 
 				reg = <0x0 0x700>;
 				clocks = <&clk26m>;
 				clock-names = "ref";
+				nvmem-cells = <&u2_intr_p1>;
+				nvmem-cell-names = "intr";
 				#phy-cells = <1>;
 			};
 
@@ -993,6 +1044,10 @@ 
 				reg = <0x700 0x700>;
 				clocks = <&clk26m>;
 				clock-names = "ref";
+				nvmem-cells = <&comb_intr_p1>,
+					      <&comb_rx_imp_p1>,
+					      <&comb_tx_imp_p1>;
+				nvmem-cell-names = "intr", "rx_imp", "tx_imp";
 				#phy-cells = <1>;
 			};
 		};
@@ -1008,6 +1063,8 @@ 
 				reg = <0x0 0x700>;
 				clocks = <&clk26m>;
 				clock-names = "ref";
+				nvmem-cells = <&u2_intr_p0>;
+				nvmem-cell-names = "intr";
 				#phy-cells = <1>;
 			};
 
@@ -1015,6 +1072,10 @@ 
 				reg = <0x700 0x700>;
 				clocks = <&clk26m>;
 				clock-names = "ref";
+				nvmem-cells = <&u3_intr_p0>,
+					      <&u3_rx_imp_p0>,
+					      <&u3_tx_imp_p0>;
+				nvmem-cell-names = "intr", "rx_imp", "tx_imp";
 				#phy-cells = <1>;
 			};
 		};