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Thu, 11 Nov 2021 02:15:19 -0800 (PST) Received: from localhost.localdomain ([2405:201:c00a:a0a9:3041:135c:4e21:846c]) by smtp.gmail.com with ESMTPSA id t12sm8035667pjo.44.2021.11.11.02.15.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Nov 2021 02:15:18 -0800 (PST) From: Jagan Teki To: Tim Harvey , Adam Ford , Fabio Estevam , Lucas Stach , Peng Fan , Shawn Guo , Marek Vasut , Frieder Schrempf Cc: NXP Linux Team , linux-arm-kernel@lists.infradead.org, dri-devel@lists.freedesktop.org, linux-amarula@amarulasolutions.com, Matteo Lisi , Jagan Teki Subject: [RFC PATCH v2 2/3] arm64: dts: imx8mm: Add MIPI DSI pipeline Date: Thu, 11 Nov 2021 15:44:55 +0530 Message-Id: <20211111101456.584061-3-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211111101456.584061-1-jagan@amarulasolutions.com> References: <20211111101456.584061-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211111_021525_772008_479E9397 X-CRM114-Status: GOOD ( 10.88 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add MIPI DSI pipeline for i.MX8MM. Video pipeline start from eLCDIF to MIPI DSI and respective Panel or Bridge on the backend side. Add support for it. Signed-off-by: Jagan Teki --- arch/arm64/boot/dts/freescale/imx8mm.dtsi | 55 +++++++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index caeb93313413..eddf3a467fd2 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -188,6 +188,12 @@ clk_ext4: clock-ext4 { clock-output-names = "clk_ext4"; }; + mipi_phy: mipi-video-phy { + compatible = "fsl,imx8mm-mipi-video-phy"; + syscon = <&disp_blk_ctrl>; + #phy-cells = <1>; + }; + psci { compatible = "arm,psci-1.0"; method = "smc"; @@ -1085,6 +1091,55 @@ lcdif: lcdif@32e00000 { interrupts = ; power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_LCDIF>; status = "disabled"; + + port { + lcdif_out_dsi: endpoint { + remote-endpoint = <&dsi_in_lcdif>; + }; + }; + }; + + dsi: dsi@32e10000 { + compatible = "fsl,imx8mm-mipi-dsim"; + reg = <0x32e10000 0x400>; + clocks = <&clk IMX8MM_CLK_DSI_CORE>, + <&clk IMX8MM_CLK_DSI_PHY_REF>; + clock-names = "bus_clk", "sclk_mipi"; + assigned-clocks = <&clk IMX8MM_CLK_DSI_CORE>, + <&clk IMX8MM_VIDEO_PLL1_OUT>, + <&clk IMX8MM_CLK_DSI_PHY_REF>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>, + <&clk IMX8MM_VIDEO_PLL1_BYPASS>, + <&clk IMX8MM_VIDEO_PLL1_OUT>; + assigned-clock-rates = <266000000>, <594000000>, <27000000>; + interrupts = ; + phys = <&mipi_phy 0>; + phy-names = "dsim"; + power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_MIPI_DSI>; + samsung,burst-clock-frequency = <891000000>; + samsung,esc-clock-frequency = <54000000>; + samsung,pll-clock-frequency = <27000000>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + dsi_in_lcdif: endpoint@0 { + reg = <0>; + remote-endpoint = <&lcdif_out_dsi>; + }; + }; + + port@1 { + reg = <1>; + }; + }; }; disp_blk_ctrl: blk-ctrl@32e28000 {