@@ -905,7 +905,8 @@ ddr-pmu@3d800000 {
usb3_phy0: usb-phy@381f0040 {
compatible = "fsl,imx8mp-usb-phy";
- reg = <0x381f0040 0x40>;
+ reg = <0x381f0040 0x40>,
+ <0x381f0000 0x20>;
clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>;
clock-names = "phy";
assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
@@ -947,7 +948,8 @@ usb_dwc3_0: usb@38100000 {
usb3_phy1: usb-phy@382f0040 {
compatible = "fsl,imx8mp-usb-phy";
- reg = <0x382f0040 0x40>;
+ reg = <0x382f0040 0x40>,
+ <0x382f0000 0x20>;
clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>;
clock-names = "phy";
assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
The USB3 glue layer has 2 areas in the register set, see RM Rev.1 section 11.2.5.2.1 GLUE_usb3 memory map: * USB3 control/status * PHY control/status Provide the memory area to the usb3_phy nodes for accessing the features in the USB3 control area. Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com> --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-)