From patchwork Thu Nov 25 12:46:02 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Pali_Roh=C3=A1r?= X-Patchwork-Id: 12693662 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 517A0C433EF for ; Thu, 25 Nov 2021 12:55:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=RZxN2q1/rqA6UGYDM1CcgWwa3vSOhFpyo1e+/p1rvsc=; b=n2LwvNsWZS/NUw L4oyQ9MJF/g1/tVoLcXn0yD37Pxtw9Ha6wwFixAMSBWc4Qj3ubiOQnYxq6YXFukTGgcJ+WQUFkieG Ubuo2XKxYbxtAUWP+CI5xAhqNscRjVL+wWf4ROdyw7Zd8XzTg+rzgAFrsl3KdfZzFK/EAYAIclvIE 0OC8OYKVCT34enVuLau6vvKOQsxOwttmcLBX9KgnHgq4l5M806bka2Y6P8kP2nVRN8j8Px8zySl4t tH81Gr1/eTEjNKkWnrzyOebCGO+pZ7G/cVSeHx9DZQFxTINaRyF/PHaSP/+OH0lM5rGFCIP0jcP0f cyWAekpNW2Vrz3vOOTBA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mqEFA-007VpB-5R; Thu, 25 Nov 2021 12:52:52 +0000 Received: from mail.kernel.org ([198.145.29.99]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mqE9D-007Sqa-86 for linux-arm-kernel@lists.infradead.org; Thu, 25 Nov 2021 12:46:45 +0000 Received: by mail.kernel.org (Postfix) with ESMTPSA id EFC5961131; Thu, 25 Nov 2021 12:46:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1637844403; bh=7IW9blK/IMJBVLWjKlB8p1LQPUnBoN7J+3jnRgIKmoI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Bln5kbB7dLx5PJDb/oLLEqvWOKQ1+NmzcCexth7QJp7mASDPM8LN05ujos6LP1die YP5RhuPz8TosihuoAqXObqM6Hz8IcdT/Rd23nd/YZP3U5KmMMqJLJg0srm3wRlrJ9z QKOj77j+j6CK2pcI/Zt/vVAuVZOXmEwrf89UzUUCdqWwJAc+T2dyiuTQT0gWExlN77 MMD50tp2zFGhA2EsXUJ8Y475YGWs66fB8DAVeGB0vMhSgHIYz9GXdls6b1IhaBIw9d Dm91B52G/O1PUO8ZcUUUT67n383bila83NW/P2IQELZGPlCpMR+I4goKC0sddc80i2 izijHrwr0gt3g== Received: by pali.im (Postfix) id B096767E; Thu, 25 Nov 2021 13:46:42 +0100 (CET) From: =?utf-8?q?Pali_Roh=C3=A1r?= To: Thomas Petazzoni , Lorenzo Pieralisi , Rob Herring , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Bjorn Helgaas , =?utf-8?q?Marek_Beh=C3=BAn?= Cc: linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 12/15] PCI: mvebu: Fix support for PCI_BRIDGE_CTL_BUS_RESET on emulated bridge Date: Thu, 25 Nov 2021 13:46:02 +0100 Message-Id: <20211125124605.25915-13-pali@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20211125124605.25915-1-pali@kernel.org> References: <20211125124605.25915-1-pali@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211125_044643_370187_F4BDCED4 X-CRM114-Status: GOOD ( 11.81 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hardware supports PCIe Hot Reset via PCIE_CTRL_OFF register. Use it for implementing PCI_BRIDGE_CTL_BUS_RESET bit of PCI_BRIDGE_CONTROL register on emulated bridge. With this change the function pci_reset_secondary_bus() starts working and can reset connected PCIe card. Signed-off-by: Pali Rohár Fixes: 1f08673eef12 ("PCI: mvebu: Convert to PCI emulated bridge config space") Cc: stable@vger.kernel.org --- drivers/pci/controller/pci-mvebu.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/drivers/pci/controller/pci-mvebu.c b/drivers/pci/controller/pci-mvebu.c index 36fbdc4f0e06..3075ea98c131 100644 --- a/drivers/pci/controller/pci-mvebu.c +++ b/drivers/pci/controller/pci-mvebu.c @@ -57,6 +57,7 @@ #define PCIE_CTRL_OFF 0x1a00 #define PCIE_CTRL_X1_MODE 0x0001 #define PCIE_CTRL_RC_MODE BIT(1) +#define PCIE_CTRL_MASTER_HOT_RESET BIT(24) #define PCIE_STAT_OFF 0x1a04 #define PCIE_STAT_BUS 0xff00 #define PCIE_STAT_DEV 0x1f0000 @@ -509,6 +510,22 @@ mvebu_pci_bridge_emul_base_conf_read(struct pci_bridge_emul *bridge, break; } + case PCI_INTERRUPT_LINE: { + /* + * From the whole 32bit register we support reading from HW only + * one bit: PCI_BRIDGE_CTL_BUS_RESET. + * Other bits are retrieved only from emulated config buffer. + */ + __le32 *cfgspace = (__le32 *)&bridge->conf; + u32 val = le32_to_cpu(cfgspace[PCI_INTERRUPT_LINE / 4]); + if (mvebu_readl(port, PCIE_CTRL_OFF) & PCIE_CTRL_MASTER_HOT_RESET) + val |= PCI_BRIDGE_CTL_BUS_RESET << 16; + else + val &= ~(PCI_BRIDGE_CTL_BUS_RESET << 16); + *value = val; + break; + } + default: return PCI_BRIDGE_EMUL_NOT_HANDLED; } @@ -617,6 +634,17 @@ mvebu_pci_bridge_emul_base_conf_write(struct pci_bridge_emul *bridge, mvebu_pcie_set_local_bus_nr(port, conf->secondary_bus); break; + case PCI_INTERRUPT_LINE: + if (mask & (PCI_BRIDGE_CTL_BUS_RESET << 16)) { + u32 ctrl = mvebu_readl(port, PCIE_CTRL_OFF); + if (new & (PCI_BRIDGE_CTL_BUS_RESET << 16)) + ctrl |= PCIE_CTRL_MASTER_HOT_RESET; + else + ctrl &= ~PCIE_CTRL_MASTER_HOT_RESET; + mvebu_writel(port, ctrl, PCIE_CTRL_OFF); + } + break; + default: break; }