From patchwork Fri Nov 26 14:43:07 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Pali_Roh=C3=A1r?= X-Patchwork-Id: 12693761 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 56D3FC433EF for ; Fri, 26 Nov 2021 14:45:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=v+BVjvWmbznR3HshbJRQwmTre3Ur/UlatxC6I8lsfvI=; b=hAysAle8WVYt7j aMpAU5JTh6sC99AGw7aA4HqE8D8H4AnBGNkcMotI3PR5EEcwAxJa9ODzbAQYMp27Ci1Af96p/HJYB xhs+AsPtD1fiZvLk+Onx0LnjfAF4CkxkKxaBQHVRI8R+aZsj694/6sG79ZsvVG8D3/5SStg3wPKMZ boKvSKJSEVMCGLxeoY6zkfBWy0cxFmLjwlLCtXNva0TjuQIZa1EHd7tsq64GWj+eJyxPMVm2Hur4O EGoFD/5AC1PyUTNZ4fv1xiHAmcSIVqSYyIu1PxOXRLqUWP4ziV7/bQ0JD8K3bjnQ4Kt1xCtdZbY+F YGXGcyJTU89oPAkLcxkw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mqcSX-00AoMY-Tj; Fri, 26 Nov 2021 14:44:18 +0000 Received: from dfw.source.kernel.org ([139.178.84.217]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mqcS8-00AoIb-Uu for linux-arm-kernel@lists.infradead.org; Fri, 26 Nov 2021 14:43:54 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 5AB9C6229F; Fri, 26 Nov 2021 14:43:52 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id CAA1EC004E1; Fri, 26 Nov 2021 14:43:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1637937832; bh=eHdxVaxHiuruMF/9Td8JoiWopFdjBhE0ZD897U8weQU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Z4wHuKmwrcGSBJwwGzCOqIi/9n7zgCfT0+vucq/Kwv1xcEtrkCshvG+dC+L+9OS6J KOA85PW+J0owUGdn7LFHypacJ3SrM8WNBk5WGqG9ZdkUgeE3ZBcHsImgpcKhjYAzAK OWGt+LR3HDKKu+uWpjEBCIvslfML7v4flRvP/yy+jJajPkpjYA5Clt5au1gTV1GGCN iLU3lS2qPABXmWbkuqaP6OTJaUh5aQWWWHismcJb0KDzCzyhsHL+hjlKRhHZ/JpOoT ICxtPjI87aOuXpr0Biw3MrwT6zZo/HLZiiGfIyIDa8Of8zgPBbXae2EQzLlK08ytn3 DsUJDpVqu8/tA== Received: by pali.im (Postfix) id 8C608EF6; Fri, 26 Nov 2021 15:43:49 +0100 (CET) From: =?utf-8?q?Pali_Roh=C3=A1r?= To: Lorenzo Pieralisi , Rob Herring , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Bjorn Helgaas , Thomas Petazzoni , Arnd Bergmann , Nathan Chancellor , Chris Packham , =?utf-8?q?Marek_Beh?= =?utf-8?q?=C3=BAn?= , =?utf-8?q?Jan_Kundr=C3=A1t?= Cc: linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/2] PCI: mvebu: Add support for compiling driver as module Date: Fri, 26 Nov 2021 15:43:07 +0100 Message-Id: <20211126144307.7568-3-pali@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20211126144307.7568-1-pali@kernel.org> References: <20211126144307.7568-1-pali@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211126_064353_098378_4A4B3004 X-CRM114-Status: GOOD ( 26.25 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Now when driver uses devm_pci_remap_iospace() function, it is possible implement ->remove() callback for unbinding device from driver. Implement mvebu_pcie_remove() callback with proper cleanup phase, drop driver's suppress_bind_attrs flag and switch type of CONFIG_PCI_MVEBU option from bool to tristate. This allows to compile pci-mvebu.c driver as loadable module pci-mvebu.ko with ability to unload it. Signed-off-by: Pali Rohár --- drivers/pci/controller/Kconfig | 2 +- drivers/pci/controller/pci-mvebu.c | 91 +++++++++++++++++++++++++----- 2 files changed, 77 insertions(+), 16 deletions(-) diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig index 93b141110537..67189bcd5d89 100644 --- a/drivers/pci/controller/Kconfig +++ b/drivers/pci/controller/Kconfig @@ -4,7 +4,7 @@ menu "PCI controller drivers" depends on PCI config PCI_MVEBU - bool "Marvell EBU PCIe controller" + tristate "Marvell EBU PCIe controller" depends on ARCH_MVEBU || ARCH_DOVE || COMPILE_TEST depends on MVEBU_MBUS depends on ARM diff --git a/drivers/pci/controller/pci-mvebu.c b/drivers/pci/controller/pci-mvebu.c index f2180e4630a1..f43492695f94 100644 --- a/drivers/pci/controller/pci-mvebu.c +++ b/drivers/pci/controller/pci-mvebu.c @@ -6,6 +6,7 @@ */ #include +#include #include #include #include @@ -145,22 +146,13 @@ static void mvebu_pcie_set_local_dev_nr(struct mvebu_pcie_port *port, int nr) mvebu_writel(port, stat, PCIE_STAT_OFF); } -/* - * Setup PCIE BARs and Address Decode Wins: - * BAR[0] -> internal registers (needed for MSI) - * BAR[1] -> covers all DRAM banks - * BAR[2] -> Disabled - * WIN[0-3] -> DRAM bank[0-3] - */ -static void mvebu_pcie_setup_wins(struct mvebu_pcie_port *port) +static void mvebu_pcie_disable_wins(struct mvebu_pcie_port *port) { - const struct mbus_dram_target_info *dram; - u32 size; int i; - dram = mv_mbus_dram_info(); + mvebu_writel(port, 0, PCIE_BAR_LO_OFF(0)); + mvebu_writel(port, 0, PCIE_BAR_HI_OFF(0)); - /* First, disable and clear BARs and windows. */ for (i = 1; i < 3; i++) { mvebu_writel(port, 0, PCIE_BAR_CTRL_OFF(i)); mvebu_writel(port, 0, PCIE_BAR_LO_OFF(i)); @@ -176,6 +168,25 @@ static void mvebu_pcie_setup_wins(struct mvebu_pcie_port *port) mvebu_writel(port, 0, PCIE_WIN5_CTRL_OFF); mvebu_writel(port, 0, PCIE_WIN5_BASE_OFF); mvebu_writel(port, 0, PCIE_WIN5_REMAP_OFF); +} + +/* + * Setup PCIE BARs and Address Decode Wins: + * BAR[0] -> internal registers (needed for MSI) + * BAR[1] -> covers all DRAM banks + * BAR[2] -> Disabled + * WIN[0-3] -> DRAM bank[0-3] + */ +static void mvebu_pcie_setup_wins(struct mvebu_pcie_port *port) +{ + const struct mbus_dram_target_info *dram; + u32 size; + int i; + + dram = mv_mbus_dram_info(); + + /* First, disable and clear BARs and windows. */ + mvebu_pcie_disable_wins(port); /* Setup windows for DDR banks. Count total DDR size on the fly. */ size = 0; @@ -1082,6 +1093,52 @@ static int mvebu_pcie_probe(struct platform_device *pdev) return pci_host_probe(bridge); } +static int mvebu_pcie_remove(struct platform_device *pdev) +{ + struct mvebu_pcie *pcie = platform_get_drvdata(pdev); + struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie); + u32 cmd; + int i; + + /* Remove PCI bus with all devices. */ + pci_lock_rescan_remove(); + pci_stop_root_bus(bridge->bus); + pci_remove_root_bus(bridge->bus); + pci_unlock_rescan_remove(); + + for (i = 0; i < pcie->nports; i++) { + struct mvebu_pcie_port *port = &pcie->ports[i]; + + if (!port->base) + continue; + + /* Disable Root Bridge I/O space, memory space and bus mastering. */ + cmd = mvebu_readl(port, PCIE_CMD_OFF); + cmd &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); + mvebu_writel(port, cmd, PCIE_CMD_OFF); + + /* Mask all interrupt sources. */ + mvebu_writel(port, 0, PCIE_MASK_OFF); + + /* Free config space for emulated root bridge. */ + pci_bridge_emul_cleanup(&port->bridge); + + /* Disable and clear BARs and windows. */ + mvebu_pcie_disable_wins(port); + + /* Delete PCIe IO and MEM windows. */ + if (port->iowin.size) + mvebu_pcie_del_windows(port, port->iowin.base, port->iowin.size); + if (port->memwin.size) + mvebu_pcie_del_windows(port, port->memwin.base, port->memwin.size); + + /* Power down card and disable clocks. Must be the last step. */ + mvebu_pcie_powerdown(port); + } + + return 0; +} + static const struct of_device_id mvebu_pcie_of_match_table[] = { { .compatible = "marvell,armada-xp-pcie", }, { .compatible = "marvell,armada-370-pcie", }, @@ -1098,10 +1155,14 @@ static struct platform_driver mvebu_pcie_driver = { .driver = { .name = "mvebu-pcie", .of_match_table = mvebu_pcie_of_match_table, - /* driver unloading/unbinding currently not supported */ - .suppress_bind_attrs = true, .pm = &mvebu_pcie_pm_ops, }, .probe = mvebu_pcie_probe, + .remove = mvebu_pcie_remove, }; -builtin_platform_driver(mvebu_pcie_driver); +module_platform_driver(mvebu_pcie_driver); + +MODULE_AUTHOR("Thomas Petazzoni "); +MODULE_AUTHOR("Pali Rohár "); +MODULE_DESCRIPTION("Marvell EBU PCIe controller"); +MODULE_LICENSE("GPL v2");