From patchwork Sun Nov 28 12:50:07 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adam Ford X-Patchwork-Id: 12693845 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 72480C433FE for ; Sun, 28 Nov 2021 12:52:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=omBifKunsUyB/CzX2fnrOoOtTAaSgL4x54vDc/BdnAc=; b=0ij+Rs/WRiYl3+ qjatz0fFE1I9FL3qZt52MdPrL+5+FIyzpsgW2S4vY3F41DYAy/dab4ZZl1/MDDCRLjaDz66ZwtkQ5 a/nu7FsScRupKFelkS9ClUy8gs750K95x1aoYp83RAKv6ac13VFhT4MxZD+LQBvYqV/cjXPFnQaiF H4XJTRQ4wK73DBnKOHFOyrJEexyzWe6ozoxqx9FeREX6WXgSEcm8zgZldskekW6X/kwR4CiihLXOx 0TmbogJP0xneG4ZS31o7jr52XfNx3svr/pO+epyw71IOujxrmcs7J8cVIiEXymPYXpcJDFzTHgXam pnW2+BKXcEBXYeBLK64g==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mrJdf-00FidN-M6; Sun, 28 Nov 2021 12:50:39 +0000 Received: from mail-io1-xd30.google.com ([2607:f8b0:4864:20::d30]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mrJdc-00Ficm-Bh for linux-arm-kernel@lists.infradead.org; Sun, 28 Nov 2021 12:50:37 +0000 Received: by mail-io1-xd30.google.com with SMTP id x10so17462856ioj.9 for ; Sun, 28 Nov 2021 04:50:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=wKZWF5gN/dipZUN6w+sfnbsbYZiCC0RMt8cpstFuDYk=; b=P21dv/dqm8upYHm/bOCW7i6n/1K0A7zXWbdZZ3uJ2FWQVg1hjVrtmYxZ4/WT/s+JMq /0zsAF/6HVeHDOqTZv4bOW/KqGpEcTY3LdXrvTn2UdzF9JvLB9WbSkWElQm9qsBNu/w9 +9eD3DZSMMGnkHLSEXPPs7TusKLvgbiG8o7o18YnTp2Bx43Fsm+xWZYiJIMndx2OYXV2 Y0cG0L8ElSWrethSdB9nnjFZvpVXANhVSBgKPbJLcBYQtBRd9QDHlera/6OcrGiUB8hC PEQz58AElQwP40bGTk6rLLjrYXtFG0Ilx61j5Iu41uU+3bPVGJcI/yLD/PevDq3AGqj8 KGuw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=wKZWF5gN/dipZUN6w+sfnbsbYZiCC0RMt8cpstFuDYk=; b=xKsvz+lNEEovbws68WzD77kbk38+jG1zoU5UwaX5PuH3TZ5Lli6bi5lxU9ISQs3lGs Y1XYj5DUwxOmUwyaykqmDoZEORJ+7l9gx9iyh4vwpcfHckyfSDdOZURvcgPW/pHL6h9/ VhyMPUn6LpZ2xTFYIDxNNl0kPmBstF9FS7xwze2sV0KrgBmon3knIeLt3v9+EEZoV2U9 H4m741zWcBwLjRFN81cytOIyt8qrFK2ee2Ot++pDKyZhc+E6e9/p+qDhqqFWcEaJWnzN Rfb4lcOXxn9AITIkc/7cNKDlhOd7+voz8vMdc+kSeONamkKutkDCdC0tW5qt8KPlFR01 Yhow== X-Gm-Message-State: AOAM533fpzYFt9/FRxtTQZQQfK6fuYMKqlWnSW76td1dLRNngPbtT/5y fbj4HrzUuMWPqpz81FaQab9NUhJAi6Ef2g== X-Google-Smtp-Source: ABdhPJyAx9Vhmg4ISue/Uqrz2MHWmExfKbzYQAv9cBQDO+gkW/TaliXI8WH2WGwashQEaqWWaX/Bhw== X-Received: by 2002:a6b:7306:: with SMTP id e6mr50335014ioh.25.1638103834952; Sun, 28 Nov 2021 04:50:34 -0800 (PST) Received: from aford-IdeaCentre-A730.lan ([2601:448:8400:9e8:2a06:17d2:47df:6c8e]) by smtp.gmail.com with ESMTPSA id j21sm6545240ila.6.2021.11.28.04.50.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Nov 2021 04:50:34 -0800 (PST) From: Adam Ford To: linux-arm-kernel@lists.infradead.org Cc: laurent.pinchart@ideasonboard.com, tharvey@gateworks.com, aford@beaconembedded.com, Adam Ford , Fabio Estevam , Lucas Stach , Rob Herring , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , NXP Linux Team , Catalin Marinas , Will Deacon , Peng Fan , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH V3 1/5] soc: imx: imx8m-blk-ctrl: Fix imx8mm mipi reset Date: Sun, 28 Nov 2021 06:50:07 -0600 Message-Id: <20211128125011.12817-1-aford173@gmail.com> X-Mailer: git-send-email 2.32.0 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211128_045036_465930_F54BDF5E X-CRM114-Status: GOOD ( 16.82 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Most of the blk-ctrl reset bits are found in one register, however there are two bits in offset 8 for pulling the MIPI DPHY out of reset and one of them needs to be set when IMX8MM_DISPBLK_PD_MIPI_CSI is brought out of reset or the MIPI_CSI hangs. Since MIPI_DSI is impacted, add the additional one for MIPI_DSI too. Fixes: 926e57c065df ("soc: imx: imx8m-blk-ctrl: add DISP blk-ctrl") Signed-off-by: Adam Ford Reviewed-by: Fabio Estevam Reviewed-by: Lucas Stach Reviewed-by: Laurent Pinchart --- V3: Split the mipi_phy_rst_mask for CSI and DSI into their respective domains. V2: Make a note that the extra register is only for Mini/Nano DISPLAY_BLK_CTRL Rename the new register to mipi_phy_rst_mask Encapsulate the edits to this register with an if-statement drivers/soc/imx/imx8m-blk-ctrl.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/soc/imx/imx8m-blk-ctrl.c b/drivers/soc/imx/imx8m-blk-ctrl.c index 519b3651d1d9..c2f076b56e24 100644 --- a/drivers/soc/imx/imx8m-blk-ctrl.c +++ b/drivers/soc/imx/imx8m-blk-ctrl.c @@ -17,6 +17,7 @@ #define BLK_SFT_RSTN 0x0 #define BLK_CLK_EN 0x4 +#define BLK_MIPI_RESET_DIV 0x8 /* Mini/Nano DISPLAY_BLK_CTRL only */ struct imx8m_blk_ctrl_domain; @@ -36,6 +37,15 @@ struct imx8m_blk_ctrl_domain_data { const char *gpc_name; u32 rst_mask; u32 clk_mask; + + /* + * i.MX8M Mini and Nano have a third DISPLAY_BLK_CTRL register + * which is used to control the reset for the MIPI Phy. + * Since it's only present in certain circumstances, + * an if-statement should be used before setting and clearing this + * register. + */ + u32 mipi_phy_rst_mask; }; #define DOMAIN_MAX_CLKS 3 @@ -78,6 +88,8 @@ static int imx8m_blk_ctrl_power_on(struct generic_pm_domain *genpd) /* put devices into reset */ regmap_clear_bits(bc->regmap, BLK_SFT_RSTN, data->rst_mask); + if (data->mipi_phy_rst_mask) + regmap_clear_bits(bc->regmap, BLK_MIPI_RESET_DIV, data->mipi_phy_rst_mask); /* enable upstream and blk-ctrl clocks to allow reset to propagate */ ret = clk_bulk_prepare_enable(data->num_clks, domain->clks); @@ -99,6 +111,8 @@ static int imx8m_blk_ctrl_power_on(struct generic_pm_domain *genpd) /* release reset */ regmap_set_bits(bc->regmap, BLK_SFT_RSTN, data->rst_mask); + if (data->mipi_phy_rst_mask) + regmap_set_bits(bc->regmap, BLK_MIPI_RESET_DIV, data->mipi_phy_rst_mask); /* disable upstream clocks */ clk_bulk_disable_unprepare(data->num_clks, domain->clks); @@ -120,6 +134,9 @@ static int imx8m_blk_ctrl_power_off(struct generic_pm_domain *genpd) struct imx8m_blk_ctrl *bc = domain->bc; /* put devices into reset and disable clocks */ + if (data->mipi_phy_rst_mask) + regmap_clear_bits(bc->regmap, BLK_MIPI_RESET_DIV, data->mipi_phy_rst_mask); + regmap_clear_bits(bc->regmap, BLK_SFT_RSTN, data->rst_mask); regmap_clear_bits(bc->regmap, BLK_CLK_EN, data->clk_mask); @@ -480,6 +497,7 @@ static const struct imx8m_blk_ctrl_domain_data imx8mm_disp_blk_ctl_domain_data[] .gpc_name = "mipi-dsi", .rst_mask = BIT(5), .clk_mask = BIT(8) | BIT(9), + .mipi_phy_rst_mask = BIT(17), }, [IMX8MM_DISPBLK_PD_MIPI_CSI] = { .name = "dispblk-mipi-csi", @@ -488,6 +506,7 @@ static const struct imx8m_blk_ctrl_domain_data imx8mm_disp_blk_ctl_domain_data[] .gpc_name = "mipi-csi", .rst_mask = BIT(3) | BIT(4), .clk_mask = BIT(10) | BIT(11), + .mipi_phy_rst_mask = BIT(16), }, };