| Message ID | 20211202095255.165797-6-herve.codina@bootlin.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | spear: Fix SPEAr3XX plgpio support | expand |
On Thu, Dec 2, 2021 at 10:53 AM Herve Codina <herve.codina@bootlin.com> wrote: > IRQ 0..7 are not supported by the driver for SPEAr320 SOC family. > > IRQ 0 is not reserved in SPEAr320 SOC (assigned to GPIOINT). > Furthermore, in SPEAr320s SOC variant, IRQ 0..6 are assigned > as follow: > IRQ 6 - NGPIO_INTR: Combined status of edge programmable > interrupts from GPIO ports > IRQ 5 - TX_OR_INTR: I2S interrupt on Transmit FIFO overrun > IRQ 4 - TX_EMP_INTR: I2S interrupt on Transmit FIFO empty > IRQ 3 - RX_OR_INTR: I2S interrupt on Receive FIFO overrun > IRQ 2 - RX_DA_INTR: I2S interrupt on data available in Receive FIFO > IRQ 1 - Reserved > IRQ 0 - GPIO_INTR: Legacy interrupt from GPIO ports > > Add support for these IRQs in SPEAr320 SOC family. > > Signed-off-by: Herve Codina <herve.codina@bootlin.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Yours, Linus Walleij
On Thu, Dec 2, 2021 at 10:52 AM Herve Codina <herve.codina@bootlin.com> wrote: > > IRQ 0..7 are not supported by the driver for SPEAr320 SOC family. > > IRQ 0 is not reserved in SPEAr320 SOC (assigned to GPIOINT). > Furthermore, in SPEAr320s SOC variant, IRQ 0..6 are assigned > as follow: > IRQ 6 - NGPIO_INTR: Combined status of edge programmable > interrupts from GPIO ports > IRQ 5 - TX_OR_INTR: I2S interrupt on Transmit FIFO overrun > IRQ 4 - TX_EMP_INTR: I2S interrupt on Transmit FIFO empty > IRQ 3 - RX_OR_INTR: I2S interrupt on Receive FIFO overrun > IRQ 2 - RX_DA_INTR: I2S interrupt on data available in Receive FIFO > IRQ 1 - Reserved > IRQ 0 - GPIO_INTR: Legacy interrupt from GPIO ports > > Add support for these IRQs in SPEAr320 SOC family. > > Signed-off-by: Herve Codina <herve.codina@bootlin.com> Acked-by: Arnd Bergmann <arnd@arndb.de> I took patches 4 and 6 into the soc tree now. Arnd
diff --git a/drivers/irqchip/spear-shirq.c b/drivers/irqchip/spear-shirq.c index 1518ba31a80c..7c17a6f643ef 100644 --- a/drivers/irqchip/spear-shirq.c +++ b/drivers/irqchip/spear-shirq.c @@ -149,6 +149,8 @@ static struct spear_shirq spear320_shirq_ras3 = { .offset = 0, .nr_irqs = 7, .mask = ((0x1 << 7) - 1) << 0, + .irq_chip = &dummy_irq_chip, + .status_reg = SPEAR320_INT_STS_MASK_REG, }; static struct spear_shirq spear320_shirq_ras1 = {
IRQ 0..7 are not supported by the driver for SPEAr320 SOC family. IRQ 0 is not reserved in SPEAr320 SOC (assigned to GPIOINT). Furthermore, in SPEAr320s SOC variant, IRQ 0..6 are assigned as follow: IRQ 6 - NGPIO_INTR: Combined status of edge programmable interrupts from GPIO ports IRQ 5 - TX_OR_INTR: I2S interrupt on Transmit FIFO overrun IRQ 4 - TX_EMP_INTR: I2S interrupt on Transmit FIFO empty IRQ 3 - RX_OR_INTR: I2S interrupt on Receive FIFO overrun IRQ 2 - RX_DA_INTR: I2S interrupt on data available in Receive FIFO IRQ 1 - Reserved IRQ 0 - GPIO_INTR: Legacy interrupt from GPIO ports Add support for these IRQs in SPEAr320 SOC family. Signed-off-by: Herve Codina <herve.codina@bootlin.com> --- drivers/irqchip/spear-shirq.c | 2 ++ 1 file changed, 2 insertions(+)