From patchwork Thu Dec 2 09:52:54 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Herve Codina X-Patchwork-Id: 12694485 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1EDE0C433EF for ; Thu, 2 Dec 2021 09:55:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=JDPCHshP5az1hDYdnPN+2YSrm2SJ168yNegQ2hUosXE=; b=t7YFVKzupjkn/l q3kYd7WUsbH7A0927c/3dyykVUIQLrzvG+3yVaaHhkI9gVO+kuAt8fjWAlgWsKtuueFklhgIZA6oX 896UncHXrOBgUV5PJTkj8Y5lBJBECffQqlMr58WPMi/tgzIjh+jLR2u0WyldbEQ7dxZ5N2Zh7vPQn G/xzSMDS2mMYXFMoDUhJNflqxrRgQiT5uUbe7tCNyV/5vQ/MnH8RTDnCcV9PuG3sLvNKGgpwPCDx7 z1+qIhUdl2CrGsKk0k/Pr2Pwxp9JZbpkHiAD+cn7+Yjz7UDbGy0s7XH6JcoD8pLaAabs3tXJ9h5BJ AwQcwS6A0qT2A7SDngSg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1msin3-00Bg9J-Lw; Thu, 02 Dec 2021 09:54:09 +0000 Received: from relay10.mail.gandi.net ([217.70.178.230]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1msimI-00Bfqo-5v for linux-arm-kernel@lists.infradead.org; Thu, 02 Dec 2021 09:53:23 +0000 Received: (Authenticated sender: herve.codina@bootlin.com) by relay10.mail.gandi.net (Postfix) with ESMTPA id D0C41240021; Thu, 2 Dec 2021 09:53:18 +0000 (UTC) From: Herve Codina To: Viresh Kumar , Shiraz Hashim , soc@kernel.org, Rob Herring , Thomas Gleixner , Marc Zyngier , Linus Walleij Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, Thomas Petazzoni , Herve Codina Subject: [PATCH 5/6] irq: spear-shirq: Add support for IRQ 0..6 Date: Thu, 2 Dec 2021 10:52:54 +0100 Message-Id: <20211202095255.165797-6-herve.codina@bootlin.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211202095255.165797-1-herve.codina@bootlin.com> References: <20211202095255.165797-1-herve.codina@bootlin.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211202_015322_388065_10488683 X-CRM114-Status: GOOD ( 11.90 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org IRQ 0..7 are not supported by the driver for SPEAr320 SOC family. IRQ 0 is not reserved in SPEAr320 SOC (assigned to GPIOINT). Furthermore, in SPEAr320s SOC variant, IRQ 0..6 are assigned as follow: IRQ 6 - NGPIO_INTR: Combined status of edge programmable interrupts from GPIO ports IRQ 5 - TX_OR_INTR: I2S interrupt on Transmit FIFO overrun IRQ 4 - TX_EMP_INTR: I2S interrupt on Transmit FIFO empty IRQ 3 - RX_OR_INTR: I2S interrupt on Receive FIFO overrun IRQ 2 - RX_DA_INTR: I2S interrupt on data available in Receive FIFO IRQ 1 - Reserved IRQ 0 - GPIO_INTR: Legacy interrupt from GPIO ports Add support for these IRQs in SPEAr320 SOC family. Signed-off-by: Herve Codina Acked-by: Linus Walleij Acked-by: Arnd Bergmann --- drivers/irqchip/spear-shirq.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/irqchip/spear-shirq.c b/drivers/irqchip/spear-shirq.c index 1518ba31a80c..7c17a6f643ef 100644 --- a/drivers/irqchip/spear-shirq.c +++ b/drivers/irqchip/spear-shirq.c @@ -149,6 +149,8 @@ static struct spear_shirq spear320_shirq_ras3 = { .offset = 0, .nr_irqs = 7, .mask = ((0x1 << 7) - 1) << 0, + .irq_chip = &dummy_irq_chip, + .status_reg = SPEAR320_INT_STS_MASK_REG, }; static struct spear_shirq spear320_shirq_ras1 = {