From patchwork Thu Dec 9 21:53:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alain Volmat X-Patchwork-Id: 12695532 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C1886C433F5 for ; Thu, 9 Dec 2021 21:55:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=mmMqCfkg74yko/LcIjwSbzrzuq/l9X1xPhsOjyQI66A=; b=SHkL9AcbvDRgXX XXC59jJ7PP1YzWbpw7VfOktGtZ5kXf1lQd8SNgHSqZ9Lv+DEcKIKzUmTxHRWkrCco6hNBPFkWJL1I Pk7Ezvrd3jIknZE8vV3xQbjbsYJXBLNet2ZmCawirM85p5nXy+I25roXqmUOhAjigRt0kWAZQKJ+/ r6BS4GVjCTDRxc94Ap7F5r6Qfs0Li75iGF7MUW4RaWQX5nD+OSJqnaT1PWOzhopFthmxGQCMvfe7Q ggMTvGVlogSBYUd/VSJHEWu9ZO5HPBzwjBBJO30TJhmp57IX0zLTddPQmoBRMHotYcIwe00TvSkwR /ubBmf0Q3eiqfYcPAvlg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mvRMn-0008QU-Kj; Thu, 09 Dec 2021 21:54:17 +0000 Received: from st43p00im-ztbu10063701.me.com ([17.58.63.178]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mvRMa-0008MT-3a for linux-arm-kernel@lists.infradead.org; Thu, 09 Dec 2021 21:54:05 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=me.com; s=1a1hai; t=1639086842; bh=NWO72/DYvMv0TFzGU2ckvMcUJaI/S0PUSHYe7+hMMss=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=xxcTCuM1e2W5HX2NbyLsWnQsbXG0doXuaykRoLATLCQ4FrRW10tx2f3TF0ABo2yLI Me5FFTo4RlXp5MKhF3K32so4Aq93M/TW9imqyNP4t70ijEqQNlfA6LNacTpNsm0U/P hW1SI58U+Z6W2zOLwMC387+SDqEs2BJkLzGN1nnOsoWMClAhkM7Ncj+M5rJgR+9iob KOk2LCBrykfqDcp722Mm0RI/L5EJSot+u1dMM21km+HQhiYJn1d9YtZ0N1gb8zwYp1 /egpBigC92pitXFiFr16WbV5Ac+DH5J5P73iFGMnCb54LVoktjy/7m2RKqrRFlF/wV SLPWuIA78FjFw== Received: from localhost (101.220.150.77.rev.sfr.net [77.150.220.101]) by st43p00im-ztbu10063701.me.com (Postfix) with ESMTPSA id A86D29A09B0; Thu, 9 Dec 2021 21:54:01 +0000 (UTC) From: Alain Volmat To: Rob Herring , linux-pci@vger.kernel.org Cc: Patrice Chotard , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Fabrice Gasnier , avolmat@me.com Subject: [PATCH 1/5] dt-bindings: pci: st-pcie: PCIe controller found on STi platforms Date: Thu, 9 Dec 2021 22:53:46 +0100 Message-Id: <20211209215350.4207-2-avolmat@me.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211209215350.4207-1-avolmat@me.com> References: <20211209215350.4207-1-avolmat@me.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.425, 18.0.790 definitions=2021-12-08_08:2021-12-08, 2021-12-08 signatures=0 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 suspectscore=0 malwarescore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 mlxscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-2009150000 definitions=main-2112090112 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211209_135404_308633_5FB654C0 X-CRM114-Status: GOOD ( 16.79 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Addition of the bindings for the Designware based PCIe controller that can be found on STi platforms such as STiH407, STiH410 or STiH418. Signed-off-by: Alain Volmat --- .../devicetree/bindings/pci/snps,dw-pcie.yaml | 2 +- .../devicetree/bindings/pci/st,st-pcie.yaml | 112 ++++++++++++++++++ 2 files changed, 113 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/pci/st,st-pcie.yaml diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml index 9ed0dfba7f89..3a92078128f7 100644 --- a/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml @@ -35,7 +35,7 @@ properties: maxItems: 5 items: enum: [ dbi, dbi2, config, atu, app, elbi, mgmt, ctrl, parf, cfg, link, - ulreg, smu, mpu, apb, phy ] + ulreg, smu, mpu, apb, phy, mem-window ] num-lanes: description: | diff --git a/Documentation/devicetree/bindings/pci/st,st-pcie.yaml b/Documentation/devicetree/bindings/pci/st,st-pcie.yaml new file mode 100644 index 000000000000..7d364202687c --- /dev/null +++ b/Documentation/devicetree/bindings/pci/st,st-pcie.yaml @@ -0,0 +1,112 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/st,st-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: PCIe RC controller on ST STi platform + +maintainers: + - Alain Volmat + +allOf: + - $ref: /schemas/pci/snps,dw-pcie.yaml# + +properties: + compatible: + const: st,stih407-pcie + + reg: + items: + - description: Controller control and status registers. + - description: PCIe configuration registers. + - description: Memory made available to the controller + + reg-names: + items: + - const: dbi + - const: config + - const: mem-window + + interrupts: + maxItems: 1 + + resets: + items: + - description: Controller reset + - description: Powerdown reset (optional) + minItems: 1 + + reset-names: + items: + - const: softreset + - const: powerdown + minItems: 1 + + phys: + maxItems: 1 + + phy-names: + const: pcie + + reset-gpios: true + + st,syscfg: + $ref: "/schemas/types.yaml#/definitions/phandle-array" + description: syscfg node phandle and offsets of the 2 registers + controlling root complex and ltssm. + +required: + - interrupts + - '#interrupt-cells' + - interrupt-map + - interrupt-map-mask + - resets + - reset-names + - phys + - phy-names + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + #include + pcie1: pcie@9b10000 { + compatible = "st,stih407-pcie"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + reg = <0x09b10000 0x1000>, + <0x3fff0000 0x10000>, + <0x40000000 0xc0000000>; + reg-names = "dbi", "config", "mem-window"; + + #interrupt-cells = <1>; + interrupts = ; + interrupt-names = "msi"; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &intc GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; + + st,syscfg = <&syscfg_core 0xdc 0xe4>; + + ranges = <0x82000000 0 0x30000000 0x30000000 0 0x05550000>, /* non-prefetchable memory */ + <0xc2000000 0 0x35550000 0x35550000 0 0x0AAA0000>; /* prefetchable memory */ + bus-range = <0x00 0xff>; + + resets = <&softreset STIH407_PCIE1_SOFTRESET>, + <&powerdown STIH407_PCIE1_POWERDOWN>; + + reset-names = "softreset", "powerdown"; + + phys = <&phy_port1 PHY_TYPE_PCIE>; + phy-names = "pcie"; + + reset-gpios = <&pio34 5 GPIO_ACTIVE_LOW>; + };