diff mbox series

arm64: dts: nitrogen8-som: correct network PHY reset

Message ID 20211211221743.1665873-1-dev@lynxeye.de (mailing list archive)
State New, archived
Headers show
Series arm64: dts: nitrogen8-som: correct network PHY reset | expand

Commit Message

Lucas Stach Dec. 11, 2021, 10:17 p.m. UTC 
Add the missing reset-gpios property to allow Linux to fully reset
the network PHY and fix the pinmux to add the neccessary pull-ups
for the PHY strap configuration.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
---
 .../arm64/boot/dts/freescale/imx8mq-nitrogen-som.dtsi | 11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

Comments

Shawn Guo Dec. 16, 2021, 5:45 a.m. UTC | #1 
On Sat, Dec 11, 2021 at 11:17:43PM +0100, Lucas Stach wrote:
> Add the missing reset-gpios property to allow Linux to fully reset
> the network PHY and fix the pinmux to add the neccessary pull-ups
> for the PHY strap configuration.
> 
> Signed-off-by: Lucas Stach <dev@lynxeye.de>

Applied, thanks!
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/freescale/imx8mq-nitrogen-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-nitrogen-som.dtsi
index 36fc428ebe30..5f27d3a17ddb 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq-nitrogen-som.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq-nitrogen-som.dtsi
@@ -69,6 +69,9 @@  ethphy0: ethernet-phy@4 {
 			reg = <4>;
 			interrupt-parent = <&gpio1>;
 			interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
+			reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
+			reset-assert-us = <10000>;
+			reset-deassert-us = <300>;
 		};
 	};
 };
@@ -191,13 +194,13 @@  MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f
 			MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f
 			MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f
 			MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
-			MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91
+			MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0xd1
 			MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91
 			MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91
 			MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91
-			MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91
-			MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9		0x19
-			MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11		0x59
+			MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0xd1
+			MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9		0x1
+			MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11		0x41
 		>;
 	};