| Message ID | 20211212181906.94062-3-romain.perier@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add timers for Mstar SoCs | expand |
Hi Romain, On Mon, 13 Dec 2021 at 03:19, Romain Perier <romain.perier@gmail.com> wrote: > > SSD20X family SoCs have an oscillator running at ~432Mhz for timer1 and > timer2, while timer0 is running at 12Mhz. I don't think this is technically true. I think the boot rom sets the divider for timer0 so that it runs at ~12MHz. I think the current change to only configure timer1 and timer2 is ok but maybe the commit message should say that timer0 is configured to be backwards compatible at boot. Cheers, Daniel
Hi Daniel,
What do you think about the following description ? : "
clocksource: msc313e: Add support for ssd20xd-based platforms
On SSD20X family SoCs bootrom sets the divider for timer0 to run at
12Mhz, while timer1 and timer2 are kept unchanged and defaut to ~432Mhz.
There are no ways to reduce or divide these clocks in the clktree.
However, These SoCs provide an internal "timer_divide" register that can
act on this input clock. This commit adds support for this register,
as timer1 and timer2 are used as clockevents these will run at 48Mhz.
Signed-off-by: Romain Perier <romain.perier@gmail.com>
"
Romain
Le mer. 15 déc. 2021 à 13:00, Daniel Palmer <daniel@0x0f.com> a écrit :
>
> Hi Romain,
>
> On Mon, 13 Dec 2021 at 03:19, Romain Perier <romain.perier@gmail.com> wrote:
> >
> > SSD20X family SoCs have an oscillator running at ~432Mhz for timer1 and
> > timer2, while timer0 is running at 12Mhz.
>
> I don't think this is technically true. I think the boot rom sets the
> divider for timer0 so that it runs at ~12MHz.
> I think the current change to only configure timer1 and timer2 is ok
> but maybe the commit message should say that timer0 is configured to
> be backwards compatible at boot.
>
> Cheers,
>
> Daniel
Hi Romain, On Fri, 17 Dec 2021 at 03:18, Romain Perier <romain.perier@gmail.com> wrote: > > Hi Daniel, > > What do you think about the following description ? : " > clocksource: msc313e: Add support for ssd20xd-based platforms > > > Signed-off-by: Romain Perier <romain.perier@gmail.com> I looked at the disassembly of the bootrom again and it doesn't look like it's set there. I think it's the hardware default for the register. I'm thinking something like this: On SSD20X family SoCs the timers are connected to a 432MHz clock instead of 12MHz that all the previous chips used. There is no way to reduce or divide these clocks in the clktree yet as we don't know exactly where the 432MHz clock comes from but it's enabled at boot. The SSD20X timers have an input clock divider within the timer itself to configure the frequency. timer0 is preconfigured at power up to run at 12MHz so it is backwards compatible and doesn't need special handling right now. timer1 and timer2 run at 432Mhz at power up so are not backward compatible. This commit adds support for the input clock divider register and sets timer1 and timer2 to run at 48Mhz for clockevents. Cheers, Daniel
diff --git a/drivers/clocksource/timer-msc313e.c b/drivers/clocksource/timer-msc313e.c index 154e73444a0c..54c54ca7c786 100644 --- a/drivers/clocksource/timer-msc313e.c +++ b/drivers/clocksource/timer-msc313e.c @@ -33,7 +33,9 @@ #define MSC313E_REG_TIMER_MAX_HIGH 0x0c #define MSC313E_REG_COUNTER_LOW 0x10 #define MSC313E_REG_COUNTER_HIGH 0x14 +#define MSC313E_REG_TIMER_DIVIDE 0x18 +#define MSC313E_CLK_DIVIDER 9 #define TIMER_SYNC_TICKS 3 #ifdef CONFIG_ARM @@ -179,6 +181,12 @@ static int __init msc313e_clkevt_init(struct device_node *np) if (ret) return ret; + if (of_device_is_compatible(np, "sstar,ssd20xd-timer")) { + to->of_clk.rate = clk_get_rate(to->of_clk.clk) / MSC313E_CLK_DIVIDER; + to->of_clk.period = DIV_ROUND_UP(to->of_clk.rate, HZ); + writew(MSC313E_CLK_DIVIDER - 1, timer_of_base(to) + MSC313E_REG_TIMER_DIVIDE); + } + msc313e_clkevt.cpumask = cpu_possible_mask; msc313e_clkevt.irq = to->of_irq.irq; to->clkevt = msc313e_clkevt; @@ -242,3 +250,4 @@ static int __init msc313e_timer_init(struct device_node *np) } TIMER_OF_DECLARE(msc313, "mstar,msc313e-timer", msc313e_timer_init); +TIMER_OF_DECLARE(ssd20xd, "sstar,ssd20xd-timer", msc313e_timer_init);
SSD20X family SoCs have an oscillator running at ~432Mhz for timer1 and timer2, while timer0 is running at 12Mhz. There are no ways to reduce or divide these clocks in the clktree. However, SSD20X SoCs provide an internal "timer_divide" register that can act on this input oscillator. This commit adds support for this register, as timer1 and timer2 are used as clockevents these will run at 48Mhz. Signed-off-by: Romain Perier <romain.perier@gmail.com> --- drivers/clocksource/timer-msc313e.c | 9 +++++++++ 1 file changed, 9 insertions(+)