From patchwork Thu Jan 6 16:03:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jim Quinlan X-Patchwork-Id: 12705520 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AD68CC433F5 for ; Thu, 6 Jan 2022 16:05:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:List-Subscribe:List-Help: List-Post:List-Archive:List-Unsubscribe:List-Id:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=TXFOVpJ95o3nh1Erb4ojLzD2UzpgfnRbCu92wM47yuo=; b=xvAyUXtrwxZsv6 1GfTrIXyqgv74GkqJD+CKvxsWa25bzzPGbn9sKZgHGRSvIXaI1wc/yznLZjRIxV8KQxPw0L+oESzR u4lbaoQ8oyOEHXz4bs1S2pJHqZMWEmlG5sQb5+/51DOyYNFiFFG3Gr9b27U3lp9j9XHt+/xOifW9e e+wADrpglcywzESsc7/te6ED/qTFqWqzOZsyq/GRkP51HrLeIaWMDdEFAtFES5EAldnd6v1L6jAgz PnLk0urbKR/BSBTvQtCMVrh2v4KulUMcxr04FE0Zsu4WZ4IVE41HrHJM4RMzWQvlrBjRO2YcJfj8u U503cnaOQvYXufFh7uIg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1n5VFE-000XCQ-IY; Thu, 06 Jan 2022 16:04:04 +0000 Received: from mail-pf1-x432.google.com ([2607:f8b0:4864:20::432]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1n5VEv-000X35-NH; Thu, 06 Jan 2022 16:03:47 +0000 Received: by mail-pf1-x432.google.com with SMTP id p37so2908571pfh.4; Thu, 06 Jan 2022 08:03:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=SdN+YJ62TXrTSxCxmD4U/e88GUhW9Xo7AMa+zjJB9y8=; b=pZSDNXVBUjpW4Vz+1npVATF5jK5aLGSV9iNcNWEoaO2Vpseob1m0TSu0aY4lU65zQd TWg2RMqFpeeIZ+YanrmFW/7Pc0N5uKfPWp7CNOfvXRIHnaijGuxUY5uE2LGJpeLqdllj zg1URwv+fmxcMuimypwigGNGBYI+bxVr58RJYs2BKW66X6KsrQn7jr2ikFTwDWFHq5wP lJY9e03IE0F1YhrJJ1C6MMRvuvpwNn5i8WYFASOCwZO4cBk0edJ4bCIE8AqzrJptMkpR qQyNrMmEgUPwlsGAxsNdiUeLLaI6DsLcvOmCWEnuLbqmAf9YAGx2U+p7fnu1yQMKRU3C ieiQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=SdN+YJ62TXrTSxCxmD4U/e88GUhW9Xo7AMa+zjJB9y8=; b=n+M34q/56tmBjBQMD5KS8U2IvIjaDFu+GvLI4vaGu7NVxpyuGKB7MB/3jt+9Ah4TVK au0FDX6Ldaw8GUz6uPvFm+/pa0kBKpdBN2WISbQe9HAvnFq5is02W80Zgjag7RVU3Ynu kTfhulwO6tG7odYYva9lT2ECqfqJawAdjRILTHt+nBeDVPgEP1A2bQGaMTQX2oAAlq3p Uk34ciPZ/lRgHnz3Kjat+PkPxbESaUuAqoNgfhN50dtP9iydvVkmjgoV3RKFpJnW5usj ezlcvaGqSDjsdCmNOIHV90gW0L3qgedEuxGx+cjDYx6S1FiZVaaq0kZ/661jOA0MvD+q xcoQ== X-Gm-Message-State: AOAM530TuplHtU4QAlzpZRvdnx8hdvxu1YsMTSgJ/gEnQr8tGPJEzot6 MRIaKEi62NVCXGJoFb2Onqc= X-Google-Smtp-Source: ABdhPJxMMul3ldncZfyDJ69TT+quVA6wkcOPZWP4sRDEUwiRE92/drHcvZyHGvZQuGQV+BIUK0wOVg== X-Received: by 2002:a63:7408:: with SMTP id p8mr48886911pgc.73.1641485025029; Thu, 06 Jan 2022 08:03:45 -0800 (PST) Received: from stbsrv-and-01.and.broadcom.net ([192.19.11.250]) by smtp.gmail.com with ESMTPSA id q19sm2376316pgb.77.2022.01.06.08.03.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Jan 2022 08:03:44 -0800 (PST) From: Jim Quinlan To: linux-pci@vger.kernel.org, Bjorn Helgaas , Nicolas Saenz Julienne , Lorenzo Pieralisi , Rob Herring , Mark Brown , bcm-kernel-feedback-list@broadcom.com, jim2101024@gmail.com, james.quinlan@broadcom.com Cc: Florian Fainelli , Rob Herring , Saenz Julienne , linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM7XXX ARM ARCHITECTURE), linux-rpi-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v11 2/7] dt-bindings: PCI: Correct brcmstb interrupts, interrupt-map. Date: Thu, 6 Jan 2022 11:03:25 -0500 Message-Id: <20220106160332.2143-3-jim2101024@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220106160332.2143-1-jim2101024@gmail.com> References: <20220106160332.2143-1-jim2101024@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220106_080345_789699_F8D84A29 X-CRM114-Status: UNSURE ( 9.67 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The "pcie" and "msi" interrupts were given the same interrupt when they are actually different. Interrupt-map only had the INTA entry; the INTB, INTC, and INTD entries are added. Signed-off-by: Jim Quinlan Acked-by: Florian Fainelli Acked-by: Rob Herring --- Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml index 1fe102743f82..22f2ef446f18 100644 --- a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml @@ -143,11 +143,15 @@ examples: #address-cells = <3>; #size-cells = <2>; #interrupt-cells = <1>; - interrupts = , + interrupts = , ; interrupt-names = "pcie", "msi"; interrupt-map-mask = <0x0 0x0 0x0 0x7>; - interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH + 0 0 0 2 &gicv2 GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH + 0 0 0 3 &gicv2 GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH + 0 0 0 4 &gicv2 GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; + msi-parent = <&pcie0>; msi-controller; ranges = <0x02000000 0x0 0xf8000000 0x6 0x00000000 0x0 0x04000000>;