From patchwork Mon Jan 10 01:50:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Marek_Beh=C3=BAn?= X-Patchwork-Id: 12708114 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B9F40C433F5 for ; Mon, 10 Jan 2022 01:56:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=LrN4aC4xBjLgk4WyHYwm87h1j6T5N31XHzcKwNRkq7I=; b=eq1fGO1zqSInjh zD39xAyPDztvIAtt9N2y0Ry7O1nUFHQq+OIMTa4LeLQuBQSfzMI1UZlYstTQgV987PqU7lpllr0zt ypah3xGpA/TwRDX10sJg3eULJCPA/1guEkTr7Ha4rqGdSuMXhbLVbBkCacc4EYXZz1XcygcJaOAZT hD3tURolCmCGsOZliVCGi7iE6KuTxrUeOvEt/Lbe3lsirwSkY5Y7aYOZ/zozEhU7CojfhiDFekCEY cDw+Hhy9onyu8QPIwhM6NqUGhjo1wnhvHKYZ/FxI6Ki7ySeL1p11roMkkVegGCv2TmXAydAp93lSg hmP+ZFaJakbJwhYrcZOg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1n6jtS-008o75-EM; Mon, 10 Jan 2022 01:54:42 +0000 Received: from ams.source.kernel.org ([2604:1380:4601:e00::1]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1n6jpj-008ljW-4e for linux-arm-kernel@lists.infradead.org; Mon, 10 Jan 2022 01:50:52 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id DFE65B8111B; Mon, 10 Jan 2022 01:50:49 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 11354C36AEF; Mon, 10 Jan 2022 01:50:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1641779448; bh=kenahD9QHhI1ZQq8ramyEU8rD91TP+pCdQ2TzwL2+08=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=rjVn1l3RG6FujezCoqPcY6xIbm2QfHQOlsxanIaMWlkGvg5FNTiRdNb6b3N9foyH1 sIfGQoWNOrXqmS4Ppoj1WRPXGiFLapIcqD+kfKEGjD84TNtX5CSbdNU/oHyLx4DYg1 JUm3pBafCtWLdR6+QZq8PNOifwao2Gi+BE2gRlKcMnte2CNYvv9CxnY1Crh97WWfWf Axu9Qw4qavXzadNtJt2yXTnZ5fDIqlJjUOPuaUqVRwOoHrAmUaM1UbAe0GQJmQ0/JN rE1fM/kaniTOULXhfQPfYOOc3xH7ts9REdwNKSMyMyH3jl8and5V291sRtPHqeHyzc 5Rjf2nUeNQl4Q== From: =?utf-8?q?Marek_Beh=C3=BAn?= To: Marc Zyngier , Lorenzo Pieralisi , Bjorn Helgaas Cc: pali@kernel.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, =?utf-8?q?Marek_Beh=C3=BAn?= Subject: [PATCH v2 12/23] PCI: aardvark: Enable MSI-X support Date: Mon, 10 Jan 2022 02:50:07 +0100 Message-Id: <20220110015018.26359-13-kabel@kernel.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220110015018.26359-1-kabel@kernel.org> References: <20220110015018.26359-1-kabel@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220109_175051_348789_22B04219 X-CRM114-Status: GOOD ( 15.19 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Pali Rohár According to PCI 3.0 specification, sending both MSI and MSI-X interrupts is done by DWORD memory write operation to doorbell message address. The write operation for MSI has zero upper 16 bits and the MSI interrupt number in the lower 16 bits, while the write operation for MSI-X contains a 32-bit value from MSI-X table. Since the driver only uses interrupt numbers from range 0..31, the upper 16 bits of the DWORD memory write operation to doorbell message address are zero even for MSI-X interrupts. Thus we can enable MSI-X interrupts. Testing proves that kernel can correctly receive MSI-X interrupts from PCIe cards which supports both MSI and MSI-X interrupts. Signed-off-by: Pali Rohár Signed-off-by: Marek Behún --- drivers/pci/controller/pci-aardvark.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c index 79102704d82f..a892f22510da 100644 --- a/drivers/pci/controller/pci-aardvark.c +++ b/drivers/pci/controller/pci-aardvark.c @@ -1344,7 +1344,7 @@ static struct irq_chip advk_msi_irq_chip = { static struct msi_domain_info advk_msi_domain_info = { .flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | - MSI_FLAG_MULTI_PCI_MSI, + MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX, .chip = &advk_msi_irq_chip, };