| Message ID | 20220112153639.12343-2-rex-bc.chen@mediatek.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | force hsa hbp hfp packets multiple of lanenum to avoid screen shift | expand |
Hi, On 12.01.2022 16:36, Rex-BC Chen wrote: > Since a HS transmission is composed of an arbitrary number > of bytes that may not be an integer multiple of lanes, some > lanes may run out of data before others. > (Defined in 6.1.3 of mipi_DSI_specification_v.01-02-00) > > However, for some DSI RX devices (for example, anx7625), > there is a limitation that packet number should be the same > on all DSI lanes. In other words, they need to end a HS at > the same time. Is it documented in anx7625 manual? Is it confirmed with hw team? If not, how it was detected? Have you tried to find workaround for it by inspecting registers, maybe it is just matter of clock gating deferral, timings or sth similar ???. > > Because this limitation is for some specific DSI RX devices, > it is more reasonable to put the enable control in these > DSI RX drivers. If DSI TX driver knows the information, > they can adjust the setting for this situation. > > Therefore, add a flag to control this situation beacuse the > mipi DSI specification is not forbidden this situation. I am not sure what you mean here. I have an impression (according t 6.1.3 of spec) that devices should allow transmission of arbitrary number of bytes, so this is bug in hw/fw. The question if it can be fixed. If not patches are welcome. > > Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> > Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org> > --- > include/drm/drm_mipi_dsi.h | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/include/drm/drm_mipi_dsi.h b/include/drm/drm_mipi_dsi.h > index 147e51b6d241..df4d15345326 100644 > --- a/include/drm/drm_mipi_dsi.h > +++ b/include/drm/drm_mipi_dsi.h > @@ -177,6 +177,8 @@ struct mipi_dsi_device_info { > * @lp_rate: maximum lane frequency for low power mode in hertz, this should > * be set to the real limits of the hardware, zero is only accepted for > * legacy drivers > + * @hs_packet_end_aligned: transfer DSI HS packets ending at the same time > + * for all DSI lanes > */ > struct mipi_dsi_device { > struct mipi_dsi_host *host; > @@ -189,6 +191,7 @@ struct mipi_dsi_device { > unsigned long mode_flags; > unsigned long hs_rate; > unsigned long lp_rate; > + bool hs_packet_end_aligned; Maybe it would be better to add another mode_flag. Regards Andrzej > }; > > #define MIPI_DSI_MODULE_PREFIX "mipi-dsi:"
Hi Andrzej Hajda, On Thu, Jan 13, 2022 at 01:14:14AM +0100, Andrzej Hajda wrote: > Hi, > > On 12.01.2022 16:36, Rex-BC Chen wrote: > > Since a HS transmission is composed of an arbitrary number > > of bytes that may not be an integer multiple of lanes, some > > lanes may run out of data before others. > > (Defined in 6.1.3 of mipi_DSI_specification_v.01-02-00) > > > > However, for some DSI RX devices (for example, anx7625), > > there is a limitation that packet number should be the same > > on all DSI lanes. In other words, they need to end a HS at > > the same time. > > > Is it documented in anx7625 manual? Is it confirmed with hw team? We have application note, and it is confirmed by designer, hw team. > > If not, how it was detected? Have you tried to find workaround for it by > inspecting registers, maybe it is just matter of clock gating deferral, > timings or sth similar ???. > > > > > Because this limitation is for some specific DSI RX devices, > > it is more reasonable to put the enable control in these > > DSI RX drivers. If DSI TX driver knows the information, > > they can adjust the setting for this situation. > > > > Therefore, add a flag to control this situation beacuse the > > mipi DSI specification is not forbidden this situation. > > > I am not sure what you mean here. > > I have an impression (according t 6.1.3 of spec) that devices should allow > transmission of arbitrary number of bytes, so this is bug in hw/fw. This is anx7625 bridge chip design limitation. > > The question if it can be fixed. If not patches are welcome. > > > > > > Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> > > Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org> > > --- > > include/drm/drm_mipi_dsi.h | 2 ++ > > 1 file changed, 2 insertions(+) > > > > diff --git a/include/drm/drm_mipi_dsi.h b/include/drm/drm_mipi_dsi.h > > index 147e51b6d241..df4d15345326 100644 > > --- a/include/drm/drm_mipi_dsi.h > > +++ b/include/drm/drm_mipi_dsi.h > > @@ -177,6 +177,8 @@ struct mipi_dsi_device_info { > > * @lp_rate: maximum lane frequency for low power mode in hertz, this should > > * be set to the real limits of the hardware, zero is only accepted for > > * legacy drivers > > + * @hs_packet_end_aligned: transfer DSI HS packets ending at the same time > > + * for all DSI lanes > > */ > > struct mipi_dsi_device { > > struct mipi_dsi_host *host; > > @@ -189,6 +191,7 @@ struct mipi_dsi_device { > > unsigned long mode_flags; > > unsigned long hs_rate; > > unsigned long lp_rate; > > + bool hs_packet_end_aligned; > > > Maybe it would be better to add another mode_flag. mode_flag should be OK. Thanks, Xin > > > Regards > > Andrzej > > > > > }; > > #define MIPI_DSI_MODULE_PREFIX "mipi-dsi:"
diff --git a/include/drm/drm_mipi_dsi.h b/include/drm/drm_mipi_dsi.h index 147e51b6d241..df4d15345326 100644 --- a/include/drm/drm_mipi_dsi.h +++ b/include/drm/drm_mipi_dsi.h @@ -177,6 +177,8 @@ struct mipi_dsi_device_info { * @lp_rate: maximum lane frequency for low power mode in hertz, this should * be set to the real limits of the hardware, zero is only accepted for * legacy drivers + * @hs_packet_end_aligned: transfer DSI HS packets ending at the same time + * for all DSI lanes */ struct mipi_dsi_device { struct mipi_dsi_host *host; @@ -189,6 +191,7 @@ struct mipi_dsi_device { unsigned long mode_flags; unsigned long hs_rate; unsigned long lp_rate; + bool hs_packet_end_aligned; }; #define MIPI_DSI_MODULE_PREFIX "mipi-dsi:"