From patchwork Wed Jan 12 15:36:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?UmV4LUJDIENoZW4gKOmZs+afj+i+sCk=?= X-Patchwork-Id: 12711551 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EEFC0C433EF for ; Wed, 12 Jan 2022 15:48:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=07P8aeit7SAms8acdMWy0YdXaOTIa80SQC68gk9u1GY=; b=tbxDSbIeTFdMWm RpoBQxuY73EVEGPLl9b59RzPXkVGH337NMi2zVPiQplPGPcmyxdWOoWt8h0OJfoLsxk3mYIQJlojO JDnEbo6J2FEFt5HqGaWeMFX0XIHjA/FOGeYCFQZBFJxzQp/9OxS7bCstunvlumY3iym+pymXP20ra s4onvcsiQTuz02IovmIQ3ErQPcc+LdA44UWHRBpw0+lwGfGVy59z60lOqgT6gSFXZnK7iCM09kB7n VtVYiaeQ0AN1WPbKwwcCfUUiN8VgPXfY9nwnyShOqp48c6oqc3DcZAQ+8bp4WAB1LpyMGGWUu8KLa UdN3nEca5bRGSKunnqPA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1n7fqb-002yyO-Kz; Wed, 12 Jan 2022 15:47:37 +0000 Received: from mailgw01.mediatek.com ([216.200.240.184]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1n7fqY-002yxU-9g; Wed, 12 Jan 2022 15:47:35 +0000 X-UUID: ba50ed99085a4ee4bc3e1244beb78f41-20220112 X-UUID: ba50ed99085a4ee4bc3e1244beb78f41-20220112 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 832652675; Wed, 12 Jan 2022 08:47:31 -0700 Received: from MTKMBS07N2.mediatek.inc (172.21.101.141) by MTKMBS62N2.mediatek.inc (172.29.193.42) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 12 Jan 2022 07:37:28 -0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 12 Jan 2022 23:37:27 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 12 Jan 2022 23:37:27 +0800 From: Rex-BC Chen To: , , , , , , , CC: , , , , , , Rex-BC Chen Subject: [v8, PATCH 1/3] drm/dsi: transfer DSI HS packets ending at the same time Date: Wed, 12 Jan 2022 23:36:37 +0800 Message-ID: <20220112153639.12343-2-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220112153639.12343-1-rex-bc.chen@mediatek.com> References: <20220112153639.12343-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220112_074734_367714_FEEA667E X-CRM114-Status: GOOD ( 12.11 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Since a HS transmission is composed of an arbitrary number of bytes that may not be an integer multiple of lanes, some lanes may run out of data before others. (Defined in 6.1.3 of mipi_DSI_specification_v.01-02-00) However, for some DSI RX devices (for example, anx7625), there is a limitation that packet number should be the same on all DSI lanes. In other words, they need to end a HS at the same time. Because this limitation is for some specific DSI RX devices, it is more reasonable to put the enable control in these DSI RX drivers. If DSI TX driver knows the information, they can adjust the setting for this situation. Therefore, add a flag to control this situation beacuse the mipi DSI specification is not forbidden this situation. Signed-off-by: Jitao Shi Reviewed-by: Chun-Kuang Hu --- include/drm/drm_mipi_dsi.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/drm/drm_mipi_dsi.h b/include/drm/drm_mipi_dsi.h index 147e51b6d241..df4d15345326 100644 --- a/include/drm/drm_mipi_dsi.h +++ b/include/drm/drm_mipi_dsi.h @@ -177,6 +177,8 @@ struct mipi_dsi_device_info { * @lp_rate: maximum lane frequency for low power mode in hertz, this should * be set to the real limits of the hardware, zero is only accepted for * legacy drivers + * @hs_packet_end_aligned: transfer DSI HS packets ending at the same time + * for all DSI lanes */ struct mipi_dsi_device { struct mipi_dsi_host *host; @@ -189,6 +191,7 @@ struct mipi_dsi_device { unsigned long mode_flags; unsigned long hs_rate; unsigned long lp_rate; + bool hs_packet_end_aligned; }; #define MIPI_DSI_MODULE_PREFIX "mipi-dsi:"