From patchwork Thu Jan 20 07:39:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guo Ren X-Patchwork-Id: 12718395 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2F18CC433F5 for ; Thu, 20 Jan 2022 07:50:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=cohNrPajKQhV4yXW4T1KHmGmv+u/1Pi7b91ozLpuw5Q=; b=CPW6goLT8pLuCw AFUdI1zN3Zf0skrRJakoQABlg2qJI1HsdZUDcXp9TDpRA6pJUYSSTaqbsc4FIueEh1dCGpO5SvRcw skIKlhyGRhf1oLoGwrMrlYK6QkQSe/SYQTaXpAR9nt2igmpizERmQpwJ0NAll74bGh+rJnwDxqyhO tPMpkWvycDBT61x1jMyvs47ooLz7atklKF6lxkhM81AYs7PpXubwZGE9h4lPaJHOhUhe0nD51K4g5 t0mcaCAq5AeURU2z1b+KDZBAxuX0bAyrSqW7Xhk89i2C6MxZLyULLPzCEML387F9n8bfkkZDJbDLy wi9GGotsK4Ur6lcX+boA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nASBe-009S8M-IA; Thu, 20 Jan 2022 07:48:50 +0000 Received: from dfw.source.kernel.org ([139.178.84.217]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nAS3q-009OJU-6q; Thu, 20 Jan 2022 07:40:48 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id BECE8616E4; Thu, 20 Jan 2022 07:40:45 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id A2DD6C340E4; Thu, 20 Jan 2022 07:40:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1642664445; bh=I1DaCsmJWZqrk2Lu9bluM5EEVQ99JKN+4wq1YE5MxNY=; h=From:To:Cc:Subject:Date:From; b=N7UT3X+ReEW5kEif7061gpNyOYbcCtcj2RaQeWcrAHIGT5QoEwq6GpJdRkJS6+NVF RDvNaSxO6cEmUPPsMpm1A1QMD6fkFfDMf6m04GH3R2aHZYhfUcz8jb7USB4+iQJEsH HjpIwUv0X2JIrEZGuVqAvY1Jddv9+pVwiM73f3JNqpy5zRb2hp2xFIt3bxnR8w2stl uJP7YnNzrsxJW6pENTmgBQsghFDQE57IZKTcaF1dC+r+qvlKLg0VBZT2wLooQYxIG9 J04gp1d1M/d24oqst/n7SnQl2CBRwpMug5z2uNu/+K+DijNkiPAl2jEpc9nJ9/wmC+ 7yyp2+eaOa5cA== From: guoren@kernel.org To: guoren@kernel.org, palmer@dabbelt.com, arnd@arndb.de, anup@brainfault.org, gregkh@linuxfoundation.org, liush@allwinnertech.com, wefu@redhat.com, drew@beagleboard.org, wangjunqiang@iscas.ac.cn, hch@lst.de, hch@infradead.org Cc: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-csky@vger.kernel.org, linux-s390@vger.kernel.org, sparclinux@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, inux-parisc@vger.kernel.org, linux-mips@vger.kernel.org, linux-arm-kernel@lists.infradead.org, x86@kernel.org, Guo Ren Subject: [PATCH V3 10/17] riscv: compat: Add elf.h implementation Date: Thu, 20 Jan 2022 15:39:03 +0800 Message-Id: <20220120073911.99857-11-guoren@kernel.org> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220119_234046_397003_B8B0EE55 X-CRM114-Status: GOOD ( 15.76 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Guo Ren Implement necessary type and macro for compat elf. See the code comment for detail. Signed-off-by: Guo Ren Signed-off-by: Guo Ren Cc: Arnd Bergmann Reviewed-by: Arnd Bergmann --- arch/riscv/include/asm/elf.h | 51 +++++++++++++++++++++++++++++++++++- 1 file changed, 50 insertions(+), 1 deletion(-) diff --git a/arch/riscv/include/asm/elf.h b/arch/riscv/include/asm/elf.h index f53c40026c7a..353b4589c79c 100644 --- a/arch/riscv/include/asm/elf.h +++ b/arch/riscv/include/asm/elf.h @@ -8,6 +8,8 @@ #ifndef _ASM_RISCV_ELF_H #define _ASM_RISCV_ELF_H +#include +#include #include #include #include @@ -18,11 +20,13 @@ */ #define ELF_ARCH EM_RISCV +#ifndef ELF_CLASS #ifdef CONFIG_64BIT #define ELF_CLASS ELFCLASS64 #else #define ELF_CLASS ELFCLASS32 #endif +#endif #define ELF_DATA ELFDATA2LSB @@ -31,6 +35,15 @@ */ #define elf_check_arch(x) ((x)->e_machine == EM_RISCV) +#ifdef CONFIG_COMPAT +/* + * Use the same code with elf_check_arch, because elf32_hdr & + * elf64_hdr e_machine's offset are different. The checker is + * a little bit simple compare to other architectures. + */ +#define compat_elf_check_arch(x) ((x)->e_machine == EM_RISCV) +#endif + #define CORE_DUMP_USE_REGSET #define ELF_EXEC_PAGESIZE (PAGE_SIZE) @@ -43,8 +56,14 @@ #define ELF_ET_DYN_BASE ((TASK_SIZE / 3) * 2) #ifdef CONFIG_64BIT +#ifdef CONFIG_COMPAT +#define STACK_RND_MASK (test_thread_flag(TIF_32BIT) ? \ + 0x7ff >> (PAGE_SHIFT - 12) : \ + 0x3ffff >> (PAGE_SHIFT - 12)) +#else #define STACK_RND_MASK (0x3ffff >> (PAGE_SHIFT - 12)) #endif +#endif /* * This yields a mask that user programs can use to figure out what * instruction set this CPU supports. This could be done in user space, @@ -60,11 +79,19 @@ extern unsigned long elf_hwcap; */ #define ELF_PLATFORM (NULL) +#define COMPAT_ELF_PLATFORM (NULL) + #ifdef CONFIG_MMU #define ARCH_DLINFO \ do { \ + /* \ + * Note that we add ulong after elf_addr_t because \ + * casting current->mm->context.vdso triggers a cast \ + * warning of cast from pointer to integer for \ + * COMPAT ELFCLASS32. \ + */ \ NEW_AUX_ENT(AT_SYSINFO_EHDR, \ - (elf_addr_t)current->mm->context.vdso); \ + (elf_addr_t)(ulong)current->mm->context.vdso); \ NEW_AUX_ENT(AT_L1I_CACHESIZE, \ get_cache_size(1, CACHE_TYPE_INST)); \ NEW_AUX_ENT(AT_L1I_CACHEGEOMETRY, \ @@ -90,4 +117,26 @@ do { \ *(struct user_regs_struct *)regs; \ } while (0); +#ifdef CONFIG_COMPAT + +/* + * FIXME: not sure SET_PERSONALITY for compat process is right! + */ +#define SET_PERSONALITY(ex) \ +do { if ((ex).e_ident[EI_CLASS] == ELFCLASS32) \ + set_thread_flag(TIF_32BIT); \ + else \ + clear_thread_flag(TIF_32BIT); \ + if (personality(current->personality) != PER_LINUX32) \ + set_personality(PER_LINUX | \ + (current->personality & (~PER_MASK))); \ +} while (0) + +#define COMPAT_ELF_ET_DYN_BASE ((TASK_SIZE_32 / 3) * 2) + +/* rv32 registers */ +typedef compat_ulong_t compat_elf_greg_t; +typedef compat_elf_greg_t compat_elf_gregset_t[ELF_NGREG]; + +#endif /* CONFIG_COMPAT */ #endif /* _ASM_RISCV_ELF_H */