From patchwork Sun Jan 23 03:33:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: qizhong cheng X-Patchwork-Id: 12720874 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EAFBCC433F5 for ; Sun, 23 Jan 2022 03:36:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:Subject:CC :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=TETEkzeS3/NHulJuqn76PAQesO52QaFRLCJ19JL0L/Y=; b=3VMoYCDSI+JNVw OM8KN7QRe94Qwfgl8cs5oIllTlPMWU2Z0wDpyVOtpgOWpn8mviJ+BbJ8s+bFgNDNEJ+k0E914RzQu HBjthiBxWOoRB4jLD5K6FSRUT7mT8M6X4gUBpSkNYUoZYmSmZQJeBoRIlxQuzEdP7FK1isNerX0hZ jIZZtK62wUZxGr7K5Eo80CKky9LARIIUI5gqlkpCxAmoG2N8BHT4fvDjE4Hvq1nbt4lvytUsE8pbh exLVzPGZBMeSrKt1wqZdYIRLRXmgy1Oa2/Yi7uGTDppUpxFR3MFxPnBLQ7r0IpGG3vV63kZFwpxsR ebcSWjalkSZxFmIPBOPA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nBTdr-000HeO-LF; Sun, 23 Jan 2022 03:34:11 +0000 Received: from mailgw01.mediatek.com ([216.200.240.184]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nBTdl-000HdT-KR; Sun, 23 Jan 2022 03:34:08 +0000 X-UUID: e0de53a40e154b8cad65ce57321d551e-20220122 X-UUID: e0de53a40e154b8cad65ce57321d551e-20220122 Received: from mtkcas67.mediatek.inc [(172.29.193.45)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1395878556; Sat, 22 Jan 2022 20:34:01 -0700 Received: from mtkexhb01.mediatek.inc (172.21.101.102) by MTKMBS62N2.mediatek.inc (172.29.193.42) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sat, 22 Jan 2022 19:34:00 -0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkexhb01.mediatek.inc (172.21.101.102) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sun, 23 Jan 2022 11:33:46 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Sun, 23 Jan 2022 11:33:46 +0800 From: qizhong cheng To: Ryder Lee , Jianjun Wang , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Bjorn Helgaas CC: , , , , , Subject: [PATCH] PCI: mediatek: Change MSI interrupt processing sequence Date: Sun, 23 Jan 2022 11:33:06 +0800 Message-ID: <20220123033306.29799-1-qizhong.cheng@mediatek.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220122_193405_702756_652253DA X-CRM114-Status: GOOD ( 10.31 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org As an edge-triggered interrupts, its interrupt status should be cleared before dispatch to the handler of device. Signed-off-by: qizhong cheng --- drivers/pci/controller/pcie-mediatek.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/pcie-mediatek.c b/drivers/pci/controller/pcie-mediatek.c index 2f3f974977a3..705ea33758b1 100644 --- a/drivers/pci/controller/pcie-mediatek.c +++ b/drivers/pci/controller/pcie-mediatek.c @@ -624,12 +624,12 @@ static void mtk_pcie_intr_handler(struct irq_desc *desc) if (status & MSI_STATUS){ unsigned long imsi_status; + /* Clear MSI interrupt status */ + writel(MSI_STATUS, port->base + PCIE_INT_STATUS); while ((imsi_status = readl(port->base + PCIE_IMSI_STATUS))) { for_each_set_bit(bit, &imsi_status, MTK_MSI_IRQS_NUM) generic_handle_domain_irq(port->inner_domain, bit); } - /* Clear MSI interrupt status */ - writel(MSI_STATUS, port->base + PCIE_INT_STATUS); } }