| Message ID | 20220126093340.18792-1-jason-jh.lin@mediatek.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | arm64: dts: mt8195: add display node for vdosys0 | expand |
Il 26/01/22 10:33, jason-jh.lin ha scritto: > Add display node for vdosys0. > > Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com> > --- > This patch depends on series [1] > [1] Add Mediatek Soc DRM (vdosys0) support for mt8195 > - https://patchwork.kernel.org/project/linux-mediatek/list/?series=608548 > > This patch is based on [2][3][4] > [2] arm64: dts: Add mediatek SoC mt8195 and evaluation board > - https://patchwork.kernel.org/project/linux-mediatek/patch/20220112114724.1953-4-tinghan.shen@mediatek.com/ > [3] arm64: dts: mt8195: add IOMMU and smi nodes > - https://patchwork.kernel.org/project/linux-mediatek/patch/20210615173233.26682-15-tinghan.shen@mediatek.com/ > [4] arm64: dts: mt8195: add gce node > - https://patchwork.kernel.org/project/linux-mediatek/patch/20220126090109.32143-1-jason-jh.lin@mediatek.com/ > --- > arch/arm64/boot/dts/mediatek/mt8195.dtsi | 123 +++++++++++++++++++++++ > 1 file changed, 123 insertions(+) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi > index d778ca598d18..cc3a9e898c77 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi > @@ -1067,5 +1067,128 @@ > reg = <0 0x1b000000 0 0x1000>; > #clock-cells = <1>; > }; > + > + ovl0: disp_ovl@1c000000 { Please be consistent with the other SoC DTs: call this ovl@1c000000 > + compatible = "mediatek,mt8195-disp-ovl", > + "mediatek,mt8192-disp-ovl"; > + reg = <0 0x1c000000 0 0x1000>; > + interrupts = <GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH 0>; > + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; > + clocks = <&vdosys0 CLK_VDO0_DISP_OVL0>; > + iommus = <&iommu_vdo M4U_PORT_L0_DISP_OVL0_RDMA0>; > + mediatek,gce-client-reg = > + <&gce0 SUBSYS_1c00XXXX 0x0000 0x1000>; > + }; > + > + rdma0: disp_rdma@1c002000 { ...this is just rdma > + compatible = "mediatek,mt8195-disp-rdma"; > + reg = <0 0x1c002000 0 0x1000>; > + interrupts = <GIC_SPI 638 IRQ_TYPE_LEVEL_HIGH 0>; > + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; > + clocks = <&vdosys0 CLK_VDO0_DISP_RDMA0>; > + iommus = <&iommu_vdo M4U_PORT_L0_DISP_RDMA0>; > + mediatek,gce-client-reg = > + <&gce0 SUBSYS_1c00XXXX 0x2000 0x1000>; > + }; > + > + color0: disp_color@1c003000 { color@... > + compatible = "mediatek,mt8195-disp-color", > + "mediatek,mt8173-disp-color"; > + reg = <0 0x1c003000 0 0x1000>; > + interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH 0>; > + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; > + clocks = <&vdosys0 CLK_VDO0_DISP_COLOR0>; > + mediatek,gce-client-reg = > + <&gce0 SUBSYS_1c00XXXX 0x3000 0x1000>; > + }; > + > + ccorr0: disp_ccorr@1c004000 { ccorr@... > + compatible = "mediatek,mt8195-disp-ccorr", > + "mediatek,mt8192-disp-ccorr"; > + reg = <0 0x1c004000 0 0x1000>; > + interrupts = <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0>; > + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; > + clocks = <&vdosys0 CLK_VDO0_DISP_CCORR0>; > + mediatek,gce-client-reg = > + <&gce0 SUBSYS_1c00XXXX 0x4000 0x1000>; > + }; > + > + aal0: disp_aal@1c005000 { aal@... > + compatible = "mediatek,mt8195-disp-aal", > + "mediatek,mt8173-disp-aal"; > + reg = <0 0x1c005000 0 0x1000>; > + interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>; > + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; > + clocks = <&vdosys0 CLK_VDO0_DISP_AAL0>; > + mediatek,gce-client-reg = > + <&gce0 SUBSYS_1c00XXXX 0x5000 0x1000>; > + }; > + > + gamma0: disp_gamma@1c006000 { gamma@... > + compatible = "mediatek,mt8195-disp-gamma", > + "mediatek,mt8173-disp-gamma"; > + reg = <0 0x1c006000 0 0x1000>; > + interrupts = <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>; > + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; > + clocks = <&vdosys0 CLK_VDO0_DISP_GAMMA0>; > + mediatek,gce-client-reg = > + <&gce0 SUBSYS_1c00XXXX 0x6000 0x1000>; > + }; > + > + dither0: disp_dither@1c007000 { dither@.... > + compatible = "mediatek,mt8195-disp-dither", > + "mediatek,mt8183-disp-dither"; > + reg = <0 0x1c007000 0 0x1000>; > + interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH 0>; > + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; > + clocks = <&vdosys0 CLK_VDO0_DISP_DITHER0>; > + mediatek,gce-client-reg = > + <&gce0 SUBSYS_1c00XXXX 0x7000 0x1000>; > + }; > + > + dsc0: disp_dsc_wrap@1c009000 { dsc@... > + compatible = "mediatek,mt8195-disp-dsc"; > + reg = <0 0x1c009000 0 0x1000>; > + interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH 0>; > + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; > + clocks = <&vdosys0 CLK_VDO0_DSC_WRAP0>; > + mediatek,gce-client-reg = > + <&gce0 SUBSYS_1c00XXXX 0x9000 0x1000>; > + }; > + > + merge0: disp_vpp_merge0@1c014000 { merge@... > + compatible = "mediatek,mt8195-disp-merge"; > + reg = <0 0x1c014000 0 0x1000>; > + interrupts = <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH 0>; > + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; > + clocks = <&vdosys0 CLK_VDO0_VPP_MERGE0>; > + mediatek,gce-client-reg = > + <&gce0 SUBSYS_1c01XXXX 0x4000 0x1000>; > + }; > + > + mutex: disp_mutex0@1c016000 { mutex@.... > + compatible = "mediatek,mt8195-disp-mutex"; > + reg = <0 0x1c016000 0 0x1000>; > + reg-names = "vdo0_mutex"; > + interrupts = <GIC_SPI 658 IRQ_TYPE_LEVEL_HIGH 0>; > + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; > + clocks = <&vdosys0 CLK_VDO0_DISP_MUTEX0>; > + clock-names = "vdo0_mutex"; > + mediatek,gce-events = > + <CMDQ_EVENT_VDO0_DISP_STREAM_DONE_0>; > + }; > + > + vdosys0: syscon@1c01a000 { > + compatible = "mediatek,mt8195-vdosys0", "syscon"; > + reg = <0 0x1c01a000 0 0x1000>; > + mboxes = <&gce0 0 CMDQ_THR_PRIO_4>; > + #clock-cells = <1>; > + }; > + > + vdosys1: syscon@1c100000 { > + compatible = "mediatek,mt8195-vdosys1", "syscon"; > + reg = <0 0x1c100000 0 0x1000>; > + #clock-cells = <1>; > + }; > }; > }; > Regards, Angelo
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index d778ca598d18..cc3a9e898c77 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -1067,5 +1067,128 @@ reg = <0 0x1b000000 0 0x1000>; #clock-cells = <1>; }; + + ovl0: disp_ovl@1c000000 { + compatible = "mediatek,mt8195-disp-ovl", + "mediatek,mt8192-disp-ovl"; + reg = <0 0x1c000000 0 0x1000>; + interrupts = <GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; + clocks = <&vdosys0 CLK_VDO0_DISP_OVL0>; + iommus = <&iommu_vdo M4U_PORT_L0_DISP_OVL0_RDMA0>; + mediatek,gce-client-reg = + <&gce0 SUBSYS_1c00XXXX 0x0000 0x1000>; + }; + + rdma0: disp_rdma@1c002000 { + compatible = "mediatek,mt8195-disp-rdma"; + reg = <0 0x1c002000 0 0x1000>; + interrupts = <GIC_SPI 638 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; + clocks = <&vdosys0 CLK_VDO0_DISP_RDMA0>; + iommus = <&iommu_vdo M4U_PORT_L0_DISP_RDMA0>; + mediatek,gce-client-reg = + <&gce0 SUBSYS_1c00XXXX 0x2000 0x1000>; + }; + + color0: disp_color@1c003000 { + compatible = "mediatek,mt8195-disp-color", + "mediatek,mt8173-disp-color"; + reg = <0 0x1c003000 0 0x1000>; + interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; + clocks = <&vdosys0 CLK_VDO0_DISP_COLOR0>; + mediatek,gce-client-reg = + <&gce0 SUBSYS_1c00XXXX 0x3000 0x1000>; + }; + + ccorr0: disp_ccorr@1c004000 { + compatible = "mediatek,mt8195-disp-ccorr", + "mediatek,mt8192-disp-ccorr"; + reg = <0 0x1c004000 0 0x1000>; + interrupts = <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; + clocks = <&vdosys0 CLK_VDO0_DISP_CCORR0>; + mediatek,gce-client-reg = + <&gce0 SUBSYS_1c00XXXX 0x4000 0x1000>; + }; + + aal0: disp_aal@1c005000 { + compatible = "mediatek,mt8195-disp-aal", + "mediatek,mt8173-disp-aal"; + reg = <0 0x1c005000 0 0x1000>; + interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; + clocks = <&vdosys0 CLK_VDO0_DISP_AAL0>; + mediatek,gce-client-reg = + <&gce0 SUBSYS_1c00XXXX 0x5000 0x1000>; + }; + + gamma0: disp_gamma@1c006000 { + compatible = "mediatek,mt8195-disp-gamma", + "mediatek,mt8173-disp-gamma"; + reg = <0 0x1c006000 0 0x1000>; + interrupts = <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; + clocks = <&vdosys0 CLK_VDO0_DISP_GAMMA0>; + mediatek,gce-client-reg = + <&gce0 SUBSYS_1c00XXXX 0x6000 0x1000>; + }; + + dither0: disp_dither@1c007000 { + compatible = "mediatek,mt8195-disp-dither", + "mediatek,mt8183-disp-dither"; + reg = <0 0x1c007000 0 0x1000>; + interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; + clocks = <&vdosys0 CLK_VDO0_DISP_DITHER0>; + mediatek,gce-client-reg = + <&gce0 SUBSYS_1c00XXXX 0x7000 0x1000>; + }; + + dsc0: disp_dsc_wrap@1c009000 { + compatible = "mediatek,mt8195-disp-dsc"; + reg = <0 0x1c009000 0 0x1000>; + interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; + clocks = <&vdosys0 CLK_VDO0_DSC_WRAP0>; + mediatek,gce-client-reg = + <&gce0 SUBSYS_1c00XXXX 0x9000 0x1000>; + }; + + merge0: disp_vpp_merge0@1c014000 { + compatible = "mediatek,mt8195-disp-merge"; + reg = <0 0x1c014000 0 0x1000>; + interrupts = <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; + clocks = <&vdosys0 CLK_VDO0_VPP_MERGE0>; + mediatek,gce-client-reg = + <&gce0 SUBSYS_1c01XXXX 0x4000 0x1000>; + }; + + mutex: disp_mutex0@1c016000 { + compatible = "mediatek,mt8195-disp-mutex"; + reg = <0 0x1c016000 0 0x1000>; + reg-names = "vdo0_mutex"; + interrupts = <GIC_SPI 658 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; + clocks = <&vdosys0 CLK_VDO0_DISP_MUTEX0>; + clock-names = "vdo0_mutex"; + mediatek,gce-events = + <CMDQ_EVENT_VDO0_DISP_STREAM_DONE_0>; + }; + + vdosys0: syscon@1c01a000 { + compatible = "mediatek,mt8195-vdosys0", "syscon"; + reg = <0 0x1c01a000 0 0x1000>; + mboxes = <&gce0 0 CMDQ_THR_PRIO_4>; + #clock-cells = <1>; + }; + + vdosys1: syscon@1c100000 { + compatible = "mediatek,mt8195-vdosys1", "syscon"; + reg = <0 0x1c100000 0 0x1000>; + #clock-cells = <1>; + }; }; };
Add display node for vdosys0. Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com> --- This patch depends on series [1] [1] Add Mediatek Soc DRM (vdosys0) support for mt8195 - https://patchwork.kernel.org/project/linux-mediatek/list/?series=608548 This patch is based on [2][3][4] [2] arm64: dts: Add mediatek SoC mt8195 and evaluation board - https://patchwork.kernel.org/project/linux-mediatek/patch/20220112114724.1953-4-tinghan.shen@mediatek.com/ [3] arm64: dts: mt8195: add IOMMU and smi nodes - https://patchwork.kernel.org/project/linux-mediatek/patch/20210615173233.26682-15-tinghan.shen@mediatek.com/ [4] arm64: dts: mt8195: add gce node - https://patchwork.kernel.org/project/linux-mediatek/patch/20220126090109.32143-1-jason-jh.lin@mediatek.com/ --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 123 +++++++++++++++++++++++ 1 file changed, 123 insertions(+)