| Message ID | 20220204133751.498600-1-tudor.ambarus@microchip.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | ARM: dts: at91: sama7g5: Add crypto nodes | expand |
On 2/4/22 15:37, Tudor Ambarus wrote: > Describe and enable the AES, SHA and TDES crypto IPs. > > Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> > --- > arch/arm/boot/dts/sama7g5.dtsi | 35 ++++++++++++++++++++++++++++++++++ > 1 file changed, 35 insertions(+) > > diff --git a/arch/arm/boot/dts/sama7g5.dtsi b/arch/arm/boot/dts/sama7g5.dtsi > index 7972cb8c2562..1f2731a64139 100644 > --- a/arch/arm/boot/dts/sama7g5.dtsi > +++ b/arch/arm/boot/dts/sama7g5.dtsi > @@ -393,6 +393,29 @@ pit64b1: timer@e1804000 { > clock-names = "pclk", "gclk"; > }; > > + aes: aes@e1810000 { > + compatible = "atmel,at91sam9g46-aes"; > + reg = <0xe1810000 0x100>; > + interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; > + dmas = <&dma0 AT91_XDMAC_DT_PERID(1)>, > + <&dma0 AT91_XDMAC_DT_PERID(2)>; > + dma-names = "tx", "rx"; > + clocks = <&pmc PMC_TYPE_PERIPHERAL 27>; > + clock-names = "aes_clk"; > + status = "okay"; > + }; > + > + sha: sha@e1814000 { > + compatible = "atmel,at91sam9g46-sha"; > + reg = <0xe1814000 0x100>; > + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; > + dmas = <&dma0 AT91_XDMAC_DT_PERID(48)>; > + dma-names = "tx"; > + clocks = <&pmc PMC_TYPE_PERIPHERAL 83>; > + clock-names = "sha_clk"; > + status = "okay"; > + }; > + > flx0: flexcom@e1818000 { > compatible = "atmel,sama5d2-flexcom"; > reg = <0xe1818000 0x200>; > @@ -475,6 +498,18 @@ trng: rng@e2010000 { > status = "disabled"; > }; > > + tdes@e2014000 { tdes: tdes@e2014000 I should have added a label here. Nicolas, maybe you can add it when applying, if everything else looks ok to you. > + compatible = "atmel,at91sam9g46-tdes"; > + reg = <0xe2014000 0x100>; > + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; > + dmas = <&dma0 AT91_XDMAC_DT_PERID(54)>, > + <&dma0 AT91_XDMAC_DT_PERID(53)>; > + dma-names = "tx", "rx"; > + clocks = <&pmc PMC_TYPE_PERIPHERAL 96>; > + clock-names = "tdes_clk"; > + status = "okay"; > + }; > + > flx4: flexcom@e2018000 { > compatible = "atmel,sama5d2-flexcom"; > reg = <0xe2018000 0x200>;
On 04/02/2022 at 18:36, Tudor Ambarus - M18064 wrote: > On 2/4/22 15:37, Tudor Ambarus wrote: >> Describe and enable the AES, SHA and TDES crypto IPs. >> >> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> >> --- >> arch/arm/boot/dts/sama7g5.dtsi | 35 ++++++++++++++++++++++++++++++++++ >> 1 file changed, 35 insertions(+) >> >> diff --git a/arch/arm/boot/dts/sama7g5.dtsi b/arch/arm/boot/dts/sama7g5.dtsi >> index 7972cb8c2562..1f2731a64139 100644 >> --- a/arch/arm/boot/dts/sama7g5.dtsi >> +++ b/arch/arm/boot/dts/sama7g5.dtsi >> @@ -393,6 +393,29 @@ pit64b1: timer@e1804000 { >> clock-names = "pclk", "gclk"; >> }; >> >> + aes: aes@e1810000 { >> + compatible = "atmel,at91sam9g46-aes"; >> + reg = <0xe1810000 0x100>; >> + interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; >> + dmas = <&dma0 AT91_XDMAC_DT_PERID(1)>, >> + <&dma0 AT91_XDMAC_DT_PERID(2)>; >> + dma-names = "tx", "rx"; >> + clocks = <&pmc PMC_TYPE_PERIPHERAL 27>; >> + clock-names = "aes_clk"; >> + status = "okay"; >> + }; >> + >> + sha: sha@e1814000 { >> + compatible = "atmel,at91sam9g46-sha"; >> + reg = <0xe1814000 0x100>; >> + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; >> + dmas = <&dma0 AT91_XDMAC_DT_PERID(48)>; >> + dma-names = "tx"; >> + clocks = <&pmc PMC_TYPE_PERIPHERAL 83>; >> + clock-names = "sha_clk"; >> + status = "okay"; >> + }; >> + >> flx0: flexcom@e1818000 { >> compatible = "atmel,sama5d2-flexcom"; >> reg = <0xe1818000 0x200>; >> @@ -475,6 +498,18 @@ trng: rng@e2010000 { >> status = "disabled"; >> }; >> >> + tdes@e2014000 { > tdes: tdes@e2014000 > > I should have added a label here. Nicolas, maybe you can add it when applying, > if everything else looks ok to you. Yep, if everything else is okay I can definitively add it when applying. Regards, Nicolas >> + compatible = "atmel,at91sam9g46-tdes"; >> + reg = <0xe2014000 0x100>; >> + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; >> + dmas = <&dma0 AT91_XDMAC_DT_PERID(54)>, >> + <&dma0 AT91_XDMAC_DT_PERID(53)>; >> + dma-names = "tx", "rx"; >> + clocks = <&pmc PMC_TYPE_PERIPHERAL 96>; >> + clock-names = "tdes_clk"; >> + status = "okay"; >> + }; >> + >> flx4: flexcom@e2018000 { >> compatible = "atmel,sama5d2-flexcom"; >> reg = <0xe2018000 0x200>; >
diff --git a/arch/arm/boot/dts/sama7g5.dtsi b/arch/arm/boot/dts/sama7g5.dtsi index 7972cb8c2562..1f2731a64139 100644 --- a/arch/arm/boot/dts/sama7g5.dtsi +++ b/arch/arm/boot/dts/sama7g5.dtsi @@ -393,6 +393,29 @@ pit64b1: timer@e1804000 { clock-names = "pclk", "gclk"; }; + aes: aes@e1810000 { + compatible = "atmel,at91sam9g46-aes"; + reg = <0xe1810000 0x100>; + interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dma0 AT91_XDMAC_DT_PERID(1)>, + <&dma0 AT91_XDMAC_DT_PERID(2)>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 27>; + clock-names = "aes_clk"; + status = "okay"; + }; + + sha: sha@e1814000 { + compatible = "atmel,at91sam9g46-sha"; + reg = <0xe1814000 0x100>; + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dma0 AT91_XDMAC_DT_PERID(48)>; + dma-names = "tx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 83>; + clock-names = "sha_clk"; + status = "okay"; + }; + flx0: flexcom@e1818000 { compatible = "atmel,sama5d2-flexcom"; reg = <0xe1818000 0x200>; @@ -475,6 +498,18 @@ trng: rng@e2010000 { status = "disabled"; }; + tdes@e2014000 { + compatible = "atmel,at91sam9g46-tdes"; + reg = <0xe2014000 0x100>; + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dma0 AT91_XDMAC_DT_PERID(54)>, + <&dma0 AT91_XDMAC_DT_PERID(53)>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 96>; + clock-names = "tdes_clk"; + status = "okay"; + }; + flx4: flexcom@e2018000 { compatible = "atmel,sama5d2-flexcom"; reg = <0xe2018000 0x200>;
Describe and enable the AES, SHA and TDES crypto IPs. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> --- arch/arm/boot/dts/sama7g5.dtsi | 35 ++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+)