From patchwork Tue Feb 8 13:42:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Stein X-Patchwork-Id: 12738802 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0CB38C433F5 for ; Tue, 8 Feb 2022 13:44:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=UCvloy/CeBl+vlx82wHcSWlktW0J9kw5Iye/UOUvYEw=; b=FLMwMGM+uYoD2i LpsYbaaUs/9Si+lAMwi6TKNCMzlkabvUaOTs0lDDsSwrqGP4tdwmS7tQwngD2LYs6plaY4rxB+SLu AcjGgyrOBSXkcWAeC4aXtyIaHBqarfje1IAy8qdmiTY3xfkiG4rPjm/W/5xb5tnwwQeqo32zsdyrd X7p7yisnZcaD51THQi1am/TVwQQeJ2e3YJ1eWgKf0TWYQxWdHBCE4alg7m+GHNq4NcPaIk5k1ZXqa ZRkCVETrdV5dr8dMDVA+6VpNGe+/XjLH/JMM5+MVN/Fprb1TpdjhzLIBgRv/quh76m/38SarovAoe oq0+KOuppEOeTu/fx6Xw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nHQmE-00EBIa-02; Tue, 08 Feb 2022 13:43:26 +0000 Received: from mx1.tq-group.com ([93.104.207.81]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nHQlT-00EB4D-8K for linux-arm-kernel@lists.infradead.org; Tue, 08 Feb 2022 13:42:42 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tq-group.com; i=@tq-group.com; q=dns/txt; s=key1; t=1644327759; x=1675863759; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=SD54LpyS0KteDVo51gmB3/be2iHRr84gbkjLTZgeado=; b=H7/TctU8q2ICKgw34BGQiRbaalDNOYZLY/v5E9DwEFrZChC2zU7x+Kal LqDI7OZRn6RafYLNBifLib0+KsMRPnLWJGETdytxE+7vN1rgNtYqAGIRk itNV7sqr0kohLnunO8fJm9MJJUMsAmtxkg70tWyQmKnrJ1sEjlqRBaWR7 9fDsdemMasZJkvjrc5rhntyyAOqUH0JKI8C07x4mTnjyhZG2ypaHtDs4T cPrjytCltC6pvzpmxpV8tsx+ZTNGoVsCoXBtM/30nWG4SOt617EqDjZt4 58cta4zxB8m71mhO/m2gNK3v5/Sb/VvrRIDj9LQdtOK/M8xiFgElNNpBf g==; X-IronPort-AV: E=Sophos;i="5.88,352,1635199200"; d="scan'208";a="21962450" Received: from unknown (HELO tq-pgp-pr1.tq-net.de) ([192.168.6.15]) by mx1-pgp.tq-group.com with ESMTP; 08 Feb 2022 14:42:31 +0100 Received: from mx1.tq-group.com ([192.168.6.7]) by tq-pgp-pr1.tq-net.de (PGP Universal service); Tue, 08 Feb 2022 14:42:31 +0100 X-PGP-Universal: processed; by tq-pgp-pr1.tq-net.de on Tue, 08 Feb 2022 14:42:31 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tq-group.com; i=@tq-group.com; q=dns/txt; s=key1; t=1644327751; x=1675863751; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=SD54LpyS0KteDVo51gmB3/be2iHRr84gbkjLTZgeado=; b=LEzcUfszSreBrkmcGmf3Km9lJeBM2o5f6W6i5kbukAJyV5M996TwbNNU 0potEMKLVqk39ZeUm9g0e51VyyxS6upa/LMpJyBIjHd2QXTk4d5tANDX5 t4OP0GqZUHBfTSxFiSIed9bBUcxwjYjBP97E2THTWluVyVhmPJSf0IGRv Bk763mzm/qzqAZsb5lyQYdyiNTOFYiyddhTNjMss0Rr/sDDTqUX3nefrc 2tdtWblvCytrSoO6g5L1q22K4cVoTpl6KMoINfwWOmUTQXq6h5xf7r+2s pA0zQATrmO7mDITytOMJIT6puRHBukwtIeuIMO6NBxGSceYU8L25xXLPQ A==; X-IronPort-AV: E=Sophos;i="5.88,352,1635199200"; d="scan'208";a="21962449" Received: from vtuxmail01.tq-net.de ([10.115.0.20]) by mx1.tq-group.com with ESMTP; 08 Feb 2022 14:42:31 +0100 Received: from steina-w.tq-net.de (unknown [10.123.49.12]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by vtuxmail01.tq-net.de (Postfix) with ESMTPSA id D3DEF280078; Tue, 8 Feb 2022 14:42:30 +0100 (CET) From: Alexander Stein To: Rob Herring , Krzysztof Kozlowski , Shawn Guo , Sascha Hauer , Fabio Estevam Cc: Alexander Stein , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 4/5] ARM: dts: imx6ull: add TQ-Systems MBa6ULLx device trees Date: Tue, 8 Feb 2022 14:42:22 +0100 Message-Id: <20220208134223.908757-5-alexander.stein@ew.tq-group.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220208134223.908757-1-alexander.stein@ew.tq-group.com> References: <20220208134223.908757-1-alexander.stein@ew.tq-group.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220208_054239_666648_06B4A279 X-CRM114-Status: GOOD ( 16.73 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add device trees for the MBa6ULx mainboard with TQMa6ULLx SoMs. Signed-off-by: Alexander Stein --- arch/arm/boot/dts/Makefile | 1 + .../boot/dts/imx6ull-tqma6ull2-mba6ulx.dts | 15 ++++ arch/arm/boot/dts/imx6ull-tqma6ull2.dtsi | 76 +++++++++++++++++++ 3 files changed, 92 insertions(+) create mode 100644 arch/arm/boot/dts/imx6ull-tqma6ull2-mba6ulx.dts create mode 100644 arch/arm/boot/dts/imx6ull-tqma6ull2.dtsi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 4112b618a539..3a6eccb6371a 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -709,6 +709,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \ imx6ull-phytec-segin-ff-rdk-nand.dtb \ imx6ull-phytec-segin-ff-rdk-emmc.dtb \ imx6ull-phytec-segin-lc-rdk-nand.dtb \ + imx6ull-tqma6ull2-mba6ulx.dtb \ imx6ulz-14x14-evk.dtb \ imx6ulz-bsh-smm-m2.dtb dtb-$(CONFIG_SOC_IMX7D) += \ diff --git a/arch/arm/boot/dts/imx6ull-tqma6ull2-mba6ulx.dts b/arch/arm/boot/dts/imx6ull-tqma6ull2-mba6ulx.dts new file mode 100644 index 000000000000..e593b7036fc7 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-tqma6ull2-mba6ulx.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2018-2022 TQ-Systems GmbH + * Author: Markus Niebel + */ + +/dts-v1/; + +#include "imx6ull-tqma6ull2.dtsi" +#include "mba6ulx.dtsi" + +/ { + model = "TQ-Systems TQMa6ULL2 SoM on MBa6ULx board"; + compatible = "tq,imx6ull-tqma6ull2-mba6ulx", "tq,imx6ull-tqma6ull2", "fsl,imx6ull"; +}; diff --git a/arch/arm/boot/dts/imx6ull-tqma6ull2.dtsi b/arch/arm/boot/dts/imx6ull-tqma6ull2.dtsi new file mode 100644 index 000000000000..326e6da91ed4 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-tqma6ull2.dtsi @@ -0,0 +1,76 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2018-2022 TQ-Systems GmbH + * Author: Markus Niebel + */ + +#include "imx6ull.dtsi" +#include "imx6ul-tqma6ul-common.dtsi" +#include "imx6ul-tqma6ulx-common.dtsi" + +/ { + model = "TQ-Systems TQMa6ULL2 SoM"; + compatible = "tq,imx6ull-tqma6ull2", "fsl,imx6ull"; +}; + +&usdhc2 { + fsl,tuning-step= <6>; + /* Errata ERR010450 Workaround */ + max-frequency = <99000000>; + assigned-clocks = <&clks IMX6UL_CLK_USDHC2_SEL>, <&clks IMX6UL_CLK_USDHC2>; + assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>; + assigned-clock-rates = <0>, <198000000>; +}; + +&iomuxc { + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x00017031 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x00017039 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x00017039 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x00017039 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x00017039 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x00017039 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x00017039 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x00017039 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x00017039 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x00017039 + /* rst */ + MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x000170f1 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x000170f1 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x000170f1 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x000170f1 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x000170f1 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x000170f1 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x000170f1 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x000170f1 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x000170f1 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x000170f1 + /* rst */ + MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x000170f1 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x000170f1 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x000170f1 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x000170f1 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x000170f1 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x000170f1 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x000170f1 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x000170f1 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x000170f1 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x000170f1 + /* rst */ + MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 + >; + }; +};