| Message ID | 20220215091224.7910-3-t.remmet@phytec.de (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | arm64: dts: phyCORE-i.MX8MP SoM updates | expand |
> -----Original Message----- > From: Teresa Remmet [mailto:t.remmet@phytec.de] > Sent: 2022年2月15日 17:12 > To: linux-arm-kernel@lists.infradead.org > Cc: Heiko Schocher <hs@denx.de>; Jonas Kuenstler <j.kuenstler@phytec.de>; > Bough Chen <haibo.chen@nxp.com>; dl-linux-imx <linux-imx@nxp.com>; > Fabio Estevam <festevam@gmail.com>; Sascha Hauer > <s.hauer@pengutronix.de>; Shawn Guo <shawnguo@kernel.org>; Rob > Herring <robh+dt@kernel.org> > Subject: [PATCH 2/7] arm64: dts: imx8mp-phycore-som: Adapt eMMC drive > strength > > Set eMMC drive strength for USDHC3_DATA lines (200Mhz) to X4 for signal > improvement. > > Signed-off-by: Teresa Remmet <t.remmet@phytec.de> Reviewed-by: Haibo Chen <haibo.chen@nxp.com> > --- > .../boot/dts/freescale/imx8mp-phycore-som.dtsi | 16 ++++++++-------- > 1 file changed, 8 insertions(+), 8 deletions(-) > > diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi > b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi > index 778f601a0119..927290990d02 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi > @@ -299,14 +299,14 @@ pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { > fsl,pins = < > MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 > MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 > - MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 > 0x1d6 > - MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 > 0x1d6 > - MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 > 0x1d6 > - MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 > 0x1d6 > - MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 > - MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 > - MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 > - MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 > + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 > 0x1d2 > + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 > 0x1d2 > + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 > 0x1d2 > + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 > 0x1d2 > + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d2 > + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d2 > + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d2 > + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d2 > MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE > 0x196 > >; > }; > -- > 2.25.1
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi index 778f601a0119..927290990d02 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi @@ -299,14 +299,14 @@ pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { fsl,pins = < MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 - MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 - MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 - MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 - MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 - MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 - MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 - MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 - MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d2 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d2 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d2 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d2 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d2 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d2 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d2 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d2 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 >; };
Set eMMC drive strength for USDHC3_DATA lines (200Mhz) to X4 for signal improvement. Signed-off-by: Teresa Remmet <t.remmet@phytec.de> --- .../boot/dts/freescale/imx8mp-phycore-som.dtsi | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-)