Message ID | 20220218091633.9368-19-allen-kh.cheng@mediatek.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | Add driver nodes for MT8192 SoC | expand |
Il 18/02/22 10:16, Allen-KH Cheng ha scritto: > Add dpi node for mt8192 SoC. > > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> > --- > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 10 ++++++++++ > 1 file changed, 10 insertions(+) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi > index 543a80252ce5..55bcbf72a366 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi > @@ -1242,6 +1242,16 @@ > power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; > }; > > + dpi0: dpi@14016000 { > + compatible = "mediatek,mt8192-dpi"; > + reg = <0 0x14016000 0 0x1000>; > + interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH 0>; > + clocks = <&mmsys CLK_MM_DPI_DPI0>, > + <&mmsys CLK_MM_DISP_DPI0>, > + <&apmixedsys CLK_APMIXED_TVDPLL>; > + clock-names = "pixel", "engine", "pll"; Please, for the same reason explained for mipi_tx0: status = "disabled"; > + }; > + > iommu0: m4u@1401d000 { > compatible = "mediatek,mt8192-m4u"; > reg = <0 0x1401d000 0 0x1000>;
On Fri, 2022-02-18 at 13:56 +0100, AngeloGioacchino Del Regno wrote: > Il 18/02/22 10:16, Allen-KH Cheng ha scritto: > > Add dpi node for mt8192 SoC. > > > > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> > > --- > > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 10 ++++++++++ > > 1 file changed, 10 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi > > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi > > index 543a80252ce5..55bcbf72a366 100644 > > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi > > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi > > @@ -1242,6 +1242,16 @@ > > power-domains = <&spm > > MT8192_POWER_DOMAIN_DISP>; > > }; > > > > + dpi0: dpi@14016000 { > > + compatible = "mediatek,mt8192-dpi"; > > + reg = <0 0x14016000 0 0x1000>; > > + interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH > > 0>; > > + clocks = <&mmsys CLK_MM_DPI_DPI0>, > > + <&mmsys CLK_MM_DISP_DPI0>, > > + <&apmixedsys CLK_APMIXED_TVDPLL>; > > + clock-names = "pixel", "engine", "pll"; > > Please, for the same reason explained for mipi_tx0: > > status = "disabled"; > Hi Angelo, Thsi is the same problem with mipi_tx0. I will update in next version. Many thanks, Allen > > + }; > > + > > iommu0: m4u@1401d000 { > > compatible = "mediatek,mt8192-m4u"; > > reg = <0 0x1401d000 0 0x1000>;
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index 543a80252ce5..55bcbf72a366 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -1242,6 +1242,16 @@ power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; }; + dpi0: dpi@14016000 { + compatible = "mediatek,mt8192-dpi"; + reg = <0 0x14016000 0 0x1000>; + interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&mmsys CLK_MM_DPI_DPI0>, + <&mmsys CLK_MM_DISP_DPI0>, + <&apmixedsys CLK_APMIXED_TVDPLL>; + clock-names = "pixel", "engine", "pll"; + }; + iommu0: m4u@1401d000 { compatible = "mediatek,mt8192-m4u"; reg = <0 0x1401d000 0 0x1000>;
Add dpi node for mt8192 SoC. Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+)