From patchwork Sat Feb 19 01:29:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Collingbourne X-Patchwork-Id: 12752125 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5458DC433EF for ; Sat, 19 Feb 2022 01:31:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:From:Subject:References: Mime-Version:Message-Id:In-Reply-To:Date:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=A4aE7DFGE6jMmHMJkWOKib/MUkJeY+RJr0fGP7QK0ZM=; b=1+X4uUNQe2bpuGUGG78l6k40aC gqmnAbz4DjHozZUbko/S8Of4uCGmylpa49sFO9gEHdkOxbg0xDLgtfeB7ZF5igcEFpRxIn9XFRpd3 YwGrLTltHpnFwm/C1XtKNny4AAGVuJ1gNOvZpNdqm7erfOHZ7tgnNfxbs5WsY3jFnXrrMN41hmbma Nvq3zZX9PvZM1kEdY9hP5hHaCMwn+z3RXMxhl6CsPSilw+GLBevVi9fzL9pkPJd0+9yPFYi1/AQyV MmDRb2+dKK5KZQSXouOPPJnYm+3QMnvaWguHGO10NOJ6Ju2JiX2IsUeoPhwOmz7lkF9xvcRDEbGrh H0qFJnjg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nLEZn-00G6fp-49; Sat, 19 Feb 2022 01:30:19 +0000 Received: from mail-yw1-x114a.google.com ([2607:f8b0:4864:20::114a]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nLEZa-00G6dE-Nb for linux-arm-kernel@lists.infradead.org; Sat, 19 Feb 2022 01:30:11 +0000 Received: by mail-yw1-x114a.google.com with SMTP id 00721157ae682-2d07ae1145aso60165377b3.4 for ; Fri, 18 Feb 2022 17:30:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=HAlYyn9KnmbmoD8rPWV1wNqJvLzz5Tpsb0HkUX4HIHw=; b=tb5C0jiJAUc+t0dRPvAiENwb0uKF7ukIlY7RFbbn/6odLTMsWDFKSufoHsC999Rade W78aZyoguLRulqKo74pOISX9hB3N19AHOi2nRoVkqaY/CCuSkal/cr1q981EJna+PUjL Da+lJWVkUQS/H0rYRq4CSE5PoEoxADt1LDLVqG3ik9DGc3ydUFLGGn/KLB7R6rIrd22c +Xiw403EeX2qPxcUJ2xm7XcKGybdMsZJD85wV2hST0NT4Cjhiu67ZNwDC9SgmvdBKTY7 gcGM2y76UC3F3HwWOdkyafrW0vyh8fNtG2icBf7cQMequz8kXq2gCumBbQkqF3QiX5cy W1tw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=HAlYyn9KnmbmoD8rPWV1wNqJvLzz5Tpsb0HkUX4HIHw=; b=PO3nYgW2vFDXq8oW9DeYF835vnBL+8v+lpNczq/zeZU75FMrqkp4kZw0RwZboQdqbQ sK8NOyTAu1FN2iVsBAevhbqXMlZ4rdM/sFj3gElrsk5ISTb7VuOxSmWbHbSlVOxnRu4/ sRu3ligA9e09frXaQrNdKMJkcdaZMHkxs3jeOgwgC8UJHxhZ7LhyD8l1VN+/Y8tDH2k/ lnK37GS/Ruda3JgvD8a51mPQzT5lGcWtO9LAAFeeOHVxDwFOFh/Hibv6EfVEcW+ykGhY dZ7UhJrpgH67XGokavZYVzWiGqVEkvx3Q7AkvoGYOqyvsnG3ZwQMZyv//Jm9qmlrTqUp 5p1w== X-Gm-Message-State: AOAM531wAqScQ/PaNHgU588sSmKCjAits4ET+glSz6l/S+M4ExqaSYHC KX1VOJ65AOCE6BuU3Xu7RS0Ymn4= X-Google-Smtp-Source: ABdhPJyXqqPv1gHzxgxRtD2X8PQLKtXIr+c5HMVFUnLMzRhNSPgnVpsajrw568Zv0/+/eyjZOTU4ppI= X-Received: from pcc-desktop.svl.corp.google.com ([2620:15c:2ce:200:4926:4660:7cdf:2d]) (user=pcc job=sendgmr) by 2002:a25:e90b:0:b0:61d:9552:6f1a with SMTP id n11-20020a25e90b000000b0061d95526f1amr9592310ybd.400.1645234204963; Fri, 18 Feb 2022 17:30:04 -0800 (PST) Date: Fri, 18 Feb 2022 17:29:45 -0800 In-Reply-To: <20220219012945.894950-1-pcc@google.com> Message-Id: <20220219012945.894950-2-pcc@google.com> Mime-Version: 1.0 References: <20220219012945.894950-1-pcc@google.com> X-Mailer: git-send-email 2.35.1.473.g83b2b277ed-goog Subject: [PATCH v5 2/2] arm64: mte: avoid clearing PSTATE.TCO on entry unless necessary From: Peter Collingbourne To: Catalin Marinas , Vincenzo Frascino , Will Deacon , Andrey Konovalov , Mark Rutland Cc: Peter Collingbourne , Evgenii Stepanov , linux-arm-kernel@lists.infradead.org, linux-mm@kvack.org X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220218_173006_801218_3491B236 X-CRM114-Status: GOOD ( 20.77 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On some microarchitectures, clearing PSTATE.TCO is expensive. Clearing TCO is only necessary if in-kernel MTE is enabled, or if MTE is enabled in the userspace process in synchronous (or, soon, asymmetric) mode, because we do not report uaccess faults to userspace in none or asynchronous modes. Therefore, adjust the kernel entry code to clear TCO only if necessary. Because it is now possible to switch to a task in which TCO needs to be clear from a task in which TCO is set, we also need to do the same thing on task switch. Signed-off-by: Peter Collingbourne Link: https://linux-review.googlesource.com/id/I52d82a580bd0500d420be501af2c35fa8c90729e Reviewed-by: Catalin Marinas --- v5: - fix header circular dependency with KASAN_GENERIC/KASAN_SW_TAGS enabled with a dependent patch v4: - some changes suggested by Catalin v3: - switch to a C implementation v2: - do the same thing in cpu_switch_to() arch/arm64/include/asm/mte.h | 22 ++++++++++++++++++++++ arch/arm64/kernel/entry-common.c | 3 +++ arch/arm64/kernel/entry.S | 7 ------- arch/arm64/kernel/mte.c | 3 +++ 4 files changed, 28 insertions(+), 7 deletions(-) diff --git a/arch/arm64/include/asm/mte.h b/arch/arm64/include/asm/mte.h index 075539f5f1c8..adcb937342f1 100644 --- a/arch/arm64/include/asm/mte.h +++ b/arch/arm64/include/asm/mte.h @@ -11,7 +11,9 @@ #ifndef __ASSEMBLY__ #include +#include #include +#include #include #include @@ -86,6 +88,26 @@ static inline int mte_ptrace_copy_tags(struct task_struct *child, #endif /* CONFIG_ARM64_MTE */ +static inline void mte_disable_tco_entry(struct task_struct *task) +{ + if (!system_supports_mte()) + return; + + /* + * Re-enable tag checking (TCO set on exception entry). This is only + * necessary if MTE is enabled in either the kernel or the userspace + * task in synchronous or asymmetric mode (SCTLR_EL1.TCF0 bit 0 is set + * for both). With MTE disabled in the kernel and disabled or + * asynchronous in userspace, tag check faults (including in uaccesses) + * are not reported, therefore there is no need to re-enable checking. + * This is beneficial on microarchitectures where re-enabling TCO is + * expensive. + */ + if (kasan_hw_tags_enabled() || + (task->thread.sctlr_user & (1UL << SCTLR_EL1_TCF0_SHIFT))) + asm volatile(SET_PSTATE_TCO(0)); +} + #ifdef CONFIG_KASAN_HW_TAGS /* Whether the MTE asynchronous mode is enabled. */ DECLARE_STATIC_KEY_FALSE(mte_async_or_asymm_mode); diff --git a/arch/arm64/kernel/entry-common.c b/arch/arm64/kernel/entry-common.c index ef7fcefb96bd..7093b578e325 100644 --- a/arch/arm64/kernel/entry-common.c +++ b/arch/arm64/kernel/entry-common.c @@ -6,6 +6,7 @@ */ #include +#include #include #include #include @@ -56,6 +57,7 @@ static void noinstr enter_from_kernel_mode(struct pt_regs *regs) { __enter_from_kernel_mode(regs); mte_check_tfsr_entry(); + mte_disable_tco_entry(current); } /* @@ -103,6 +105,7 @@ static __always_inline void __enter_from_user_mode(void) CT_WARN_ON(ct_state() != CONTEXT_USER); user_exit_irqoff(); trace_hardirqs_off_finish(); + mte_disable_tco_entry(current); } static __always_inline void enter_from_user_mode(struct pt_regs *regs) diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S index 772ec2ecf488..e1013a83d4f0 100644 --- a/arch/arm64/kernel/entry.S +++ b/arch/arm64/kernel/entry.S @@ -308,13 +308,6 @@ alternative_if ARM64_HAS_IRQ_PRIO_MASKING msr_s SYS_ICC_PMR_EL1, x20 alternative_else_nop_endif - /* Re-enable tag checking (TCO set on exception entry) */ -#ifdef CONFIG_ARM64_MTE -alternative_if ARM64_MTE - SET_PSTATE_TCO(0) -alternative_else_nop_endif -#endif - /* * Registers that may be useful after this macro is invoked: * diff --git a/arch/arm64/kernel/mte.c b/arch/arm64/kernel/mte.c index f418ebc65f95..f983795b5eda 100644 --- a/arch/arm64/kernel/mte.c +++ b/arch/arm64/kernel/mte.c @@ -253,6 +253,9 @@ void mte_thread_switch(struct task_struct *next) mte_update_sctlr_user(next); mte_update_gcr_excl(next); + /* TCO may not have been disabled on exception entry for the current task. */ + mte_disable_tco_entry(next); + /* * Check if an async tag exception occurred at EL1. *