From patchwork Tue Feb 22 07:09:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Stein X-Patchwork-Id: 12754599 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E06E6C433EF for ; Tue, 22 Feb 2022 07:11:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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bh=U0dx42iOhSJjNbk7A4uPQPT68VVVNQaf6K8v5iWBqbM=; b=DYgRFcFiLVB8UypfOm0RmJv5XvM/thV9UcBZ9AOG9zydFStaSKcEPcHY BHpxt3dm1X+Ycq+RLFmeMbdDUR/nf00mFEfNFtuPFbPk0TqKhGlAtJyNt VSaqyZVokcpQvuVPCRWuHbXtxhi7GAIMIdZDQ+w4mTLeyyOxc6y/GTP8W GHZxNjWtmxvJA5W7ld+QLDlnNpzRHPZV6jgWqzQt0lU7OzXBmCO3jLnWp AzJgibFexsYVebnskmGw46jaoZxJKnk8c4YpID6495U+rx8EmuGZCmDhI lXyXfrOu2LkuLno91u2iumgdhluojR4TeDraUqUvOD8sRSfi0JhG9IXS5 Q==; X-IronPort-AV: E=Sophos;i="5.88,387,1635199200"; d="scan'208";a="22225725" Received: from vtuxmail01.tq-net.de ([10.115.0.20]) by mx1.tq-group.com with ESMTP; 22 Feb 2022 08:09:54 +0100 Received: from steina-w.tq-net.de (unknown [10.123.49.12]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by vtuxmail01.tq-net.de (Postfix) with ESMTPSA id 551FF280075; Tue, 22 Feb 2022 08:09:54 +0100 (CET) From: Alexander Stein To: Rob Herring , Krzysztof Kozlowski , Shawn Guo , Sascha Hauer , Fabio Estevam Cc: Alexander Stein , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 3/5] ARM: dts: imx6ul: add TQ-Systems MBa6ULxL device trees Date: Tue, 22 Feb 2022 08:09:43 +0100 Message-Id: <20220222070945.563672-4-alexander.stein@ew.tq-group.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220222070945.563672-1-alexander.stein@ew.tq-group.com> References: <20220222070945.563672-1-alexander.stein@ew.tq-group.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220221_230959_071825_19813C67 X-CRM114-Status: GOOD ( 17.72 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add device trees for the MBa6ULx mainboard with TQMa6ULxL SoMs. Signed-off-by: Alexander Stein --- Changes in v3: * None arch/arm/boot/dts/Makefile | 1 + .../arm/boot/dts/imx6ul-tqma6ul2l-mba6ulx.dts | 15 ++++ arch/arm/boot/dts/imx6ul-tqma6ul2l.dtsi | 71 +++++++++++++++++++ .../arm/boot/dts/imx6ul-tqma6ulxl-common.dtsi | 48 +++++++++++++ 4 files changed, 135 insertions(+) create mode 100644 arch/arm/boot/dts/imx6ul-tqma6ul2l-mba6ulx.dts create mode 100644 arch/arm/boot/dts/imx6ul-tqma6ul2l.dtsi create mode 100644 arch/arm/boot/dts/imx6ul-tqma6ulxl-common.dtsi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index ce4673e270a2..4112b618a539 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -688,6 +688,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \ imx6ul-liteboard.dtb \ imx6ul-tqma6ul1-mba6ulx.dtb \ imx6ul-tqma6ul2-mba6ulx.dtb \ + imx6ul-tqma6ul2l-mba6ulx.dtb \ imx6ul-opos6uldev.dtb \ imx6ul-pico-dwarf.dtb \ imx6ul-pico-hobbit.dtb \ diff --git a/arch/arm/boot/dts/imx6ul-tqma6ul2l-mba6ulx.dts b/arch/arm/boot/dts/imx6ul-tqma6ul2l-mba6ulx.dts new file mode 100644 index 000000000000..9d9b6b744a1c --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-tqma6ul2l-mba6ulx.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2018-2022 TQ Systems GmbH + * Author: Markus Niebel + */ + +/dts-v1/; + +#include "imx6ul-tqma6ul2l.dtsi" +#include "mba6ulx.dtsi" + +/ { + model = "TQ Systems TQMa6UL2L SoM on MBa6ULx board"; + compatible = "tq,imx6ul-tqma6ul2l-mba6ulx", "tq,imx6ul-tqma6ul2l", "fsl,imx6ul"; +}; diff --git a/arch/arm/boot/dts/imx6ul-tqma6ul2l.dtsi b/arch/arm/boot/dts/imx6ul-tqma6ul2l.dtsi new file mode 100644 index 000000000000..caf2c5d03f7e --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-tqma6ul2l.dtsi @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2018-2022 TQ-Systems GmbH + * Author: Markus Niebel + */ + +#include "imx6ul.dtsi" +#include "imx6ul-tqma6ul-common.dtsi" +#include "imx6ul-tqma6ulxl-common.dtsi" + +/ { + model = "TQ-Systems TQMa6UL2L SoM"; + compatible = "tq,imx6ul-tqma6ul2l", "fsl,imx6ul"; +}; + +&usdhc2 { + fsl,tuning-step= <6>; +}; + +&iomuxc { + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x00017051 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x00017051 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x00017051 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x00017051 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x00017051 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x00017051 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x00017051 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x00017051 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x00017051 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x00017051 + /* rst */ + MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x000170e1 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x000170f1 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x000170f1 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x000170f1 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x000170f1 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x000170f1 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x000170f1 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x000170f1 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x000170f1 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x000170f1 + /* rst */ + MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x000170f9 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x000170f1 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x000170f1 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x000170f1 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x000170f1 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x000170f1 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x000170f1 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x000170f1 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x000170f1 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x000170f1 + /* rst */ + MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6ul-tqma6ulxl-common.dtsi b/arch/arm/boot/dts/imx6ul-tqma6ulxl-common.dtsi new file mode 100644 index 000000000000..ba84a4f70ebd --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-tqma6ulxl-common.dtsi @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2018-2022 TQ-Systems GmbH + * Author: Markus Niebel + */ + +/* + * Common for + * - TQMa6ULxL + * - TQMa6ULLxL + */ + +/ { + reg_vin: reg-vin { + compatible = "regulator-fixed"; + regulator-name = "VIN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; +}; + +&m24c64_50 { + vcc-supply = <®_vin>; +}; + +&m24c02_52 { + vcc-supply = <®_vin>; +}; + +/* eMMC */ +&usdhc2 { + vmmc-supply = <®_vin>; + vqmmc-supply = <®_vldo4>; +}; + +&iomuxc { + pinctrl_qspi: qspigrp { + fsl,pins = < + MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a9 + MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a9 + MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a9 + MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a9 + MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a9 + MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1 + >; + }; +};