Message ID | 20220222163158.1666-4-pali@kernel.org (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | PCI: mvebu: Slot support | expand |
On Tue, 22 Feb 2022 17:31:55 +0100 Pali Rohár <pali@kernel.org> wrote: > This property specifies slot power limit in mW unit. It is a form-factor > and board specific value and must be initialized by hardware. > > Some PCIe controllers delegate this work to software to allow hardware > flexibility and therefore this property basically specifies what should > host bridge program into PCIe Slot Capabilities registers. > > The property needs to be specified in mW unit instead of the special format > defined by Slot Capabilities (which encodes scaling factor or different > unit). Host drivers should convert the value from mW to needed format. > > Signed-off-by: Pali Rohár <pali@kernel.org> > Signed-off-by: Marek Behún <kabel@kernel.org> This patch is not needed, the property already is described in dtschema. Marek
On Tuesday 22 February 2022 18:24:15 Marek Behún wrote: > On Tue, 22 Feb 2022 17:31:55 +0100 > Pali Rohár <pali@kernel.org> wrote: > > > This property specifies slot power limit in mW unit. It is a form-factor > > and board specific value and must be initialized by hardware. > > > > Some PCIe controllers delegate this work to software to allow hardware > > flexibility and therefore this property basically specifies what should > > host bridge program into PCIe Slot Capabilities registers. > > > > The property needs to be specified in mW unit instead of the special format > > defined by Slot Capabilities (which encodes scaling factor or different > > unit). Host drivers should convert the value from mW to needed format. > > > > Signed-off-by: Pali Rohár <pali@kernel.org> > > Signed-off-by: Marek Behún <kabel@kernel.org> > > This patch is not needed, the property already is described in > dtschema. But dtschema with this property is not included in kernel and this file is the only in-kernel documentation. So updating it makes sense.
diff --git a/Documentation/devicetree/bindings/pci/pci.txt b/Documentation/devicetree/bindings/pci/pci.txt index 6a8f2874a24d..b0cc133ed00d 100644 --- a/Documentation/devicetree/bindings/pci/pci.txt +++ b/Documentation/devicetree/bindings/pci/pci.txt @@ -32,6 +32,12 @@ driver implementation may support the following properties: root port to downstream device and host bridge drivers can do programming which depends on CLKREQ signal existence. For example, programming root port not to advertise ASPM L1 Sub-States support if there is no CLKREQ signal. +- slot-power-limit-milliwatt: + If present, this property specifies slot power limit in milliwatts. Host + drivers can parse this property and use it for programming Root Port or host + bridge, or for composing and sending PCIe Set_Slot_Power_Limit messages + through the Root Port or host bridge when transitioning PCIe link from a + non-DL_Up Status to a DL_Up Status. PCI-PCI Bridge properties -------------------------