| Message ID | 20220228132523.2679099-1-michael@walle.cc (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | arm64: dts: imx8mn-evk: add QSPI flash | expand |
Hi Michael Am Mo., 28. Feb. 2022 um 14:25 Uhr schrieb Michael Walle <michael@walle.cc>: > > There is a 32MiB Micron MT25QU256ABA1 serial NOR flash on the EVK board. > Add a device tree node for it. > > Tested on a 8MNANOD3L-EVK. > > Signed-off-by: Michael Walle <michael@walle.cc> Tested-by: Heiko Thiery <heiko.thiery@gmail.com> > --- > arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi | 27 +++++++++++++++++++ > 1 file changed, 27 insertions(+) > > diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi > index c3f15192b76c..dc75d6d13bb3 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi > @@ -110,6 +110,22 @@ vddio: vddio-regulator { > }; > }; > > +&flexspi { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_flexspi>; > + status = "okay"; > + > + flash0: flash@0 { > + compatible = "jedec,spi-nor"; > + reg = <0>; > + #address-cells = <1>; > + #size-cells = <1>; > + spi-max-frequency = <166000000>; > + spi-tx-bus-width = <4>; > + spi-rx-bus-width = <4>; > + }; > +}; > + > &i2c1 { > clock-frequency = <400000>; > pinctrl-names = "default"; > @@ -267,6 +283,17 @@ MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19 > >; > }; > > + pinctrl_flexspi: flexspigrp { > + fsl,pins = < > + MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2 > + MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 > + MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 > + MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 > + MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 > + MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 > + >; > + }; > + > pinctrl_gpio_led: gpioledgrp { > fsl,pins = < > MX8MN_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 > -- > 2.30.2 >
On Mon, Feb 28, 2022 at 02:25:23PM +0100, Michael Walle wrote: > There is a 32MiB Micron MT25QU256ABA1 serial NOR flash on the EVK board. > Add a device tree node for it. > > Tested on a 8MNANOD3L-EVK. > > Signed-off-by: Michael Walle <michael@walle.cc> Applied, thanks!
diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi index c3f15192b76c..dc75d6d13bb3 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi @@ -110,6 +110,22 @@ vddio: vddio-regulator { }; }; +&flexspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi>; + status = "okay"; + + flash0: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <166000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + &i2c1 { clock-frequency = <400000>; pinctrl-names = "default"; @@ -267,6 +283,17 @@ MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19 >; }; + pinctrl_flexspi: flexspigrp { + fsl,pins = < + MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2 + MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 + MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 + MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 + MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 + MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 + >; + }; + pinctrl_gpio_led: gpioledgrp { fsl,pins = < MX8MN_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19
There is a 32MiB Micron MT25QU256ABA1 serial NOR flash on the EVK board. Add a device tree node for it. Tested on a 8MNANOD3L-EVK. Signed-off-by: Michael Walle <michael@walle.cc> --- arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi | 27 +++++++++++++++++++ 1 file changed, 27 insertions(+)