| Message ID | 20220303160323.3316317-3-michael@walle.cc (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | ARM: dts: lan966x: dtsi improvements and KSwitch D10 support | expand |
On 03.03.2022 18:03, Michael Walle wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe > > Add the device tree node for the SGPIO IP block reused from the > SparX-5. Keep the node disabled by default. > > Signed-off-by: Michael Walle <michael@walle.cc> > --- > arch/arm/boot/dts/lan966x.dtsi | 26 ++++++++++++++++++++++++++ > 1 file changed, 26 insertions(+) > > diff --git a/arch/arm/boot/dts/lan966x.dtsi b/arch/arm/boot/dts/lan966x.dtsi > index 5e9cbc8cdcbc..a7d46a2ca058 100644 > --- a/arch/arm/boot/dts/lan966x.dtsi > +++ b/arch/arm/boot/dts/lan966x.dtsi > @@ -223,6 +223,32 @@ gpio: pinctrl@e2004064 { > #interrupt-cells = <2>; > }; > > + sgpio: gpio@e2004190 { > + #address-cells = <1>; > + #size-cells = <0>; > + compatible = "microchip,sparx5-sgpio"; > + clocks = <&sys_clk>; > + reg = <0xe2004190 0x118>; > + status = "disabled"; > + > + sgpio_in: gpio@0 { > + reg = <0>; > + compatible = "microchip,sparx5-sgpio-bank"; > + gpio-controller; > + #gpio-cells = <3>; > + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-controller; > + #interrupt-cells = <3>; Can you preserve the order or properties for this node > + }; > + > + sgpio_out: gpio@1 { > + compatible = "microchip,sparx5-sgpio-bank"; > + reg = <1>; > + gpio-controller; > + #gpio-cells = <3>; and this node. It would be easier to follow it. As a note I see most of the nodes in this DT follows the order: - compatible - reg For consistency with the rest of the nodes it would be good to keep the same order here. > + }; > + }; > + > gic: interrupt-controller@e8c11000 { > compatible = "arm,gic-400", "arm,cortex-a7-gic"; > #interrupt-cells = <3>; > -- > 2.30.2 >
diff --git a/arch/arm/boot/dts/lan966x.dtsi b/arch/arm/boot/dts/lan966x.dtsi index 5e9cbc8cdcbc..a7d46a2ca058 100644 --- a/arch/arm/boot/dts/lan966x.dtsi +++ b/arch/arm/boot/dts/lan966x.dtsi @@ -223,6 +223,32 @@ gpio: pinctrl@e2004064 { #interrupt-cells = <2>; }; + sgpio: gpio@e2004190 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "microchip,sparx5-sgpio"; + clocks = <&sys_clk>; + reg = <0xe2004190 0x118>; + status = "disabled"; + + sgpio_in: gpio@0 { + reg = <0>; + compatible = "microchip,sparx5-sgpio-bank"; + gpio-controller; + #gpio-cells = <3>; + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <3>; + }; + + sgpio_out: gpio@1 { + compatible = "microchip,sparx5-sgpio-bank"; + reg = <1>; + gpio-controller; + #gpio-cells = <3>; + }; + }; + gic: interrupt-controller@e8c11000 { compatible = "arm,gic-400", "arm,cortex-a7-gic"; #interrupt-cells = <3>;
Add the device tree node for the SGPIO IP block reused from the SparX-5. Keep the node disabled by default. Signed-off-by: Michael Walle <michael@walle.cc> --- arch/arm/boot/dts/lan966x.dtsi | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+)