diff mbox series

[v3,19/21] arm64: dts: mt8192: Add dsi node

Message ID 20220304130809.12924-20-allen-kh.cheng@mediatek.com (mailing list archive)
State New, archived
Headers show
Series Add driver nodes for MT8192 SoC | expand

Commit Message

Allen-KH Cheng March 4, 2022, 1:08 p.m. UTC 
Add dsi ndoe for mt8192 SoC.

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

Comments

AngeloGioacchino Del Regno March 15, 2022, 2:51 p.m. UTC | #1 
Il 04/03/22 14:08, Allen-KH Cheng ha scritto:
> Add dsi ndoe for mt8192 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> ---
>   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 14 ++++++++++++++
>   1 file changed, 14 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 94f88e52776b..3d16cb0b3ea1 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -1327,6 +1327,20 @@
>   			clocks = <&mmsys CLK_MM_DISP_DITHER0>;
>   		};
>   
> +		dsi0: dsi@14010000 {
> +			compatible = "mediatek,mt8183-dsi";
> +			reg = <0 0x14010000 0 0x1000>;
> +			interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>;
> +			mediatek,syscon-dsi = <&mmsys 0x140>;

mediatek,syscon-dsi does not exist upstream: here we have proper reset controller
support.

> +			clocks = <&mmsys CLK_MM_DSI0>,
> +				 <&mmsys CLK_MM_DSI_DSI0>,
> +				 <&mipi_tx0>;
> +			clock-names = "engine", "digital", "hs";
> +			phys = <&mipi_tx0>;
> +			phy-names = "dphy";

On MT8183, we do....
resets = <&mmsys MT8183_MMSYS_SW0_RST_B_DISP_DSI0>;

...so you need to simply replicate for MT8192. Please do.

> +			status = "disabled";
> +		};
> +
>   		ovl_2l2: ovl@14014000 {
>   			compatible = "mediatek,mt8192-disp-ovl-2l";
>   			reg = <0 0x14014000 0 0x1000>;
Allen-KH Cheng March 18, 2022, 12:15 p.m. UTC | #2 
Hi Angelo,

On Tue, 2022-03-15 at 15:51 +0100, AngeloGioacchino Del Regno wrote:
> Il 04/03/22 14:08, Allen-KH Cheng ha scritto:
> > Add dsi ndoe for mt8192 SoC.
> > 
> > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > ---
> >   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 14 ++++++++++++++
> >   1 file changed, 14 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > index 94f88e52776b..3d16cb0b3ea1 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > @@ -1327,6 +1327,20 @@
> >   			clocks = <&mmsys CLK_MM_DISP_DITHER0>;
> >   		};
> >   
> > +		dsi0: dsi@14010000 {
> > +			compatible = "mediatek,mt8183-dsi";
> > +			reg = <0 0x14010000 0 0x1000>;
> > +			interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > +			mediatek,syscon-dsi = <&mmsys 0x140>;
> 
> mediatek,syscon-dsi does not exist upstream: here we have proper
> reset controller
> support.
> 
> > +			clocks = <&mmsys CLK_MM_DSI0>,
> > +				 <&mmsys CLK_MM_DSI_DSI0>,
> > +				 <&mipi_tx0>;
> > +			clock-names = "engine", "digital", "hs";
> > +			phys = <&mipi_tx0>;
> > +			phy-names = "dphy";
> 
> On MT8183, we do....
> resets = <&mmsys MT8183_MMSYS_SW0_RST_B_DISP_DSI0>;
> 

I'll change it at next version.

Thanks.

Best regards,
Allen

> ...so you need to simply replicate for MT8192. Please do.
> 
> > +			status = "disabled";
> > +		};
> > +
> >   		ovl_2l2: ovl@14014000 {
> >   			compatible = "mediatek,mt8192-disp-ovl-2l";
> >   			reg = <0 0x14014000 0 0x1000>;
> 
>
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 94f88e52776b..3d16cb0b3ea1 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -1327,6 +1327,20 @@ 
 			clocks = <&mmsys CLK_MM_DISP_DITHER0>;
 		};
 
+		dsi0: dsi@14010000 {
+			compatible = "mediatek,mt8183-dsi";
+			reg = <0 0x14010000 0 0x1000>;
+			interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>;
+			mediatek,syscon-dsi = <&mmsys 0x140>;
+			clocks = <&mmsys CLK_MM_DSI0>,
+				 <&mmsys CLK_MM_DSI_DSI0>,
+				 <&mipi_tx0>;
+			clock-names = "engine", "digital", "hs";
+			phys = <&mipi_tx0>;
+			phy-names = "dphy";
+			status = "disabled";
+		};
+
 		ovl_2l2: ovl@14014000 {
 			compatible = "mediatek,mt8192-disp-ovl-2l";
 			reg = <0 0x14014000 0 0x1000>;