From patchwork Tue Mar 8 20:49:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mike Leach X-Patchwork-Id: 12774370 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AD8E9C433EF for ; Tue, 8 Mar 2022 20:52:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:List-Subscribe:List-Help: List-Post:List-Archive:List-Unsubscribe:List-Id:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=mqQxeeK34Uqpy+OgaJDH5tEgKX8CZJHGRryr4aKcBg0=; b=HOBlaXur5ZYWyk RjiVYAIZVADtBkIa+xiXQmudDtNYxarHtxj8tSczN27mgsimxzrIpmikrWxbgn3d+FQQfydpIS41B Gl1Q0Q8LibRkhde/qSdjZXQidK9yOuewAcmsVnb3AtHE+DceKNaITzAlXxOFCeprtFfCQbVqwrYCl zjd7vpJSbkz+ez/5/V0Oxf1RXBjHxZd5YbH8u8FIjwJOTM/8ruavdOveFZGG2B8r1rMfQv3fbWTsi 8YHDcbL/m8MiqAa7CuYSed4FtwTAIkVqaT2pIuoe1TbWTttZHZDOihx7aNfMCZr7FPkIAQ8wpwPYh rWWASeuzTT4w04e7qqpQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nRgn8-006C44-G6; Tue, 08 Mar 2022 20:50:46 +0000 Received: from mail-wr1-x42c.google.com ([2a00:1450:4864:20::42c]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nRgmX-006Bnk-6l for linux-arm-kernel@lists.infradead.org; Tue, 08 Mar 2022 20:50:11 +0000 Received: by mail-wr1-x42c.google.com with SMTP id t11so30437020wrm.5 for ; Tue, 08 Mar 2022 12:50:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=oYqW9DzD5vwTM1HoTzl1M8XZ0WUdjZwmOMUBLoaQedw=; b=kwI9hOE21xzvlIG6kdrnHeuEPF6g66blY3CFHrAc2UD8TeLvKhI54dUHCtSErqPWlE 5w1WxnMEH4u+uohEKCsPAAUqDzUdksImLm/W/JBEgRJmbrnlOLdk5jh5/+zlOfoxndrx 65dV41IyvoBzSlGLjXT7yKpFHl+E7YkVy1oa2YYMabq6+tYyCe2LeA4zxeRwG+HafaxU nvng3fPDRjKUzxZlKe0qQwmYcvLo+UWJLv2cZcRP7VM1nckq9rLT2Tp/sLrToNM7Xy9Y v6WBC47e65Yp72Py5aI/LefiN2/wqEnj+6E6gjl/AILmt2SchXe3uUycBx4hwKvnNEvz t20A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=oYqW9DzD5vwTM1HoTzl1M8XZ0WUdjZwmOMUBLoaQedw=; b=2QqD7MQ5UjPSRI2CSBBL+RuB5+bkRFD/D8ojBAaY9wXcwytzlQvw4ye7me9xSFU7CL ahZbTJ+K6JXvnYJQ1qOTYcY3ILpP/w5oK3h/j8I80hwtOA9GFjG11ZsHpaQAgkMSoZlq Ls6qa0SqUx3yHc2U/UpyEj41+xoXAWG/EVXhej7NfChTda+Xspku6ZoTsg56DNig2jWM F7F4pATcFfs5QW7quDzT3NonBsuE08DSAQFFNiswizKfhV/oPTT98TUsBT0Y63MRuJWW xBarjzywhrx6DNQ/pGau5krUrp0QOpvHBiA31eYaGvddRj8lU3bocy3b6Qk5tbGa3f1j dT+w== X-Gm-Message-State: AOAM531fV2DXjSX/6rUTEF4ToEnhc6+z6RKyHBzmiZsCSjb8Y/q0cvks lW35peQMkEPNhgp2zAyJK6LKCA== X-Google-Smtp-Source: ABdhPJzKg0st+pjq2d0t8XXWYDVKnWlRHCW0ZEWuOCuqNDzl8hjHvkNfLUxdT3Aupg7aNHVRMe8zHA== X-Received: by 2002:a5d:68c3:0:b0:1f0:4b40:90f with SMTP id p3-20020a5d68c3000000b001f04b40090fmr13434737wrw.443.1646772607455; Tue, 08 Mar 2022 12:50:07 -0800 (PST) Received: from linaro.org ([2a00:23c5:6809:2201:546d:7d59:1703:bf96]) by smtp.gmail.com with ESMTPSA id p26-20020a1c741a000000b00389ab9a53c8sm3245758wmc.36.2022.03.08.12.50.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Mar 2022 12:50:07 -0800 (PST) From: Mike Leach To: suzuki.poulose@arm.com, coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: mathieu.poirier@linaro.org, peterz@infradead.org, mingo@redhat.com, acme@kernel.org, linux-perf-users@vger.kernel.org, leo.yan@linaro.org, Mike Leach Subject: [PATCH 03/10] coresight: stm: Update STM driver to use Trace ID api Date: Tue, 8 Mar 2022 20:49:53 +0000 Message-Id: <20220308205000.27646-4-mike.leach@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220308205000.27646-1-mike.leach@linaro.org> References: <20220308205000.27646-1-mike.leach@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220308_125009_286115_A00F3122 X-CRM114-Status: GOOD ( 20.55 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Updates the STM driver to use the trace ID allocation API. This uses the _system_id calls to allocate an ID on device poll, and release on device remove. The sysfs access to the STMTRACEIDR register has been changed from RW to RO. Having this value as writable is not appropriate for the new Trace ID scheme - and had potential to cause errors in the previous scheme if values clashed with other sources. Signed-off-by: Mike Leach --- drivers/hwtracing/coresight/coresight-stm.c | 41 +++++++-------------- 1 file changed, 14 insertions(+), 27 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-stm.c b/drivers/hwtracing/coresight/coresight-stm.c index bb14a3a8a921..6c2c29ae99fe 100644 --- a/drivers/hwtracing/coresight/coresight-stm.c +++ b/drivers/hwtracing/coresight/coresight-stm.c @@ -31,6 +31,7 @@ #include #include "coresight-priv.h" +#include "coresight-trace-id.h" #define STMDMASTARTR 0xc04 #define STMDMASTOPR 0xc08 @@ -615,24 +616,7 @@ static ssize_t traceid_show(struct device *dev, val = drvdata->traceid; return sprintf(buf, "%#lx\n", val); } - -static ssize_t traceid_store(struct device *dev, - struct device_attribute *attr, - const char *buf, size_t size) -{ - int ret; - unsigned long val; - struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent); - - ret = kstrtoul(buf, 16, &val); - if (ret) - return ret; - - /* traceid field is 7bit wide on STM32 */ - drvdata->traceid = val & 0x7f; - return size; -} -static DEVICE_ATTR_RW(traceid); +static DEVICE_ATTR_RO(traceid); #define coresight_stm_reg(name, offset) \ coresight_simple_reg32(struct stm_drvdata, name, offset) @@ -819,14 +803,6 @@ static void stm_init_default_data(struct stm_drvdata *drvdata) */ drvdata->stmsper = ~0x0; - /* - * The trace ID value for *ETM* tracers start at CPU_ID * 2 + 0x10 and - * anything equal to or higher than 0x70 is reserved. Since 0x00 is - * also reserved the STM trace ID needs to be higher than 0x00 and - * lowner than 0x10. - */ - drvdata->traceid = 0x1; - /* Set invariant transaction timing on all channels */ bitmap_clear(drvdata->chs.guaranteed, 0, drvdata->numsp); } @@ -854,7 +830,7 @@ static void stm_init_generic_data(struct stm_drvdata *drvdata, static int stm_probe(struct amba_device *adev, const struct amba_id *id) { - int ret; + int ret, trace_id; void __iomem *base; struct device *dev = &adev->dev; struct coresight_platform_data *pdata = NULL; @@ -938,12 +914,22 @@ static int stm_probe(struct amba_device *adev, const struct amba_id *id) goto stm_unregister; } + trace_id = coresight_trace_id_get_system_id(coresight_get_trace_id_map()); + if (trace_id < 0) { + ret = trace_id; + goto cs_unregister; + } + drvdata->traceid = (u8)trace_id; + pm_runtime_put(&adev->dev); dev_info(&drvdata->csdev->dev, "%s initialized\n", (char *)coresight_get_uci_data(id)); return 0; +cs_unregister: + coresight_unregister(drvdata->csdev); + stm_unregister: stm_unregister_device(&drvdata->stm); return ret; @@ -953,6 +939,7 @@ static void stm_remove(struct amba_device *adev) { struct stm_drvdata *drvdata = dev_get_drvdata(&adev->dev); + coresight_trace_id_put_system_id(coresight_get_trace_id_map(), drvdata->traceid); coresight_unregister(drvdata->csdev); stm_unregister_device(&drvdata->stm);