From patchwork Tue Mar 8 20:49:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mike Leach X-Patchwork-Id: 12774371 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 11B4DC433F5 for ; Tue, 8 Mar 2022 20:52:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:List-Subscribe:List-Help: List-Post:List-Archive:List-Unsubscribe:List-Id:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=u3RPRFPheNt1dNV6MGfNP8fVmtNUCyLWlJRrDt2WgwU=; b=w5Ie0RHsfhImaf UXflyKZduSozwupuekXX57xfD9ITG9ouYTjd8iiZH72ymrmylu8ILtn/8GMhcRjf+fg0kc4NQXpi8 NwOkSlDPL0L1o5bjpsnChO/LgOMa/xaZD58y2JVYe+ce9xZUKmcKxhPLpOhmq7nY1y1i+yU0bgGUr va4qgvnOVtNbSDfIgwtxmECT1UDRfcHAE2y6bwrTaGQ9gzF8L2imd4HTqckOJvoPa3Qfo4eHtWkDj 6kxrkAUFYBl2iS1XrjKzWIp+gPTtF+6ZQBUqE+cDD/SMKc8wkFFmeC+ee227uG9FKNIzOUVSDEsfF So5ShA838ASZYBGVYrtg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nRgnO-006CAw-1Y; Tue, 08 Mar 2022 20:51:02 +0000 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nRgmY-006BoF-19 for linux-arm-kernel@lists.infradead.org; Tue, 08 Mar 2022 20:50:13 +0000 Received: by mail-wm1-x329.google.com with SMTP id n33-20020a05600c3ba100b003832caf7f3aso2004413wms.0 for ; Tue, 08 Mar 2022 12:50:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=PHSx/CGWMYUlu4wfKzSTY+tbrWqGA6GP82ZeBxk1Lzk=; b=FFxv76yzgplTv6GmbwjqP2KTAP0fO1pv6j9vKEfaNA7rjuHxVYNoqcO/hv3Kd38I6N 8V6f5WCHhE4xVDac3cAJ09smoBshtV2NA7Dz8jS2aWwm1e5QX0dUlN8+T5Ob4pYgidUr C8MyOlY/Cd4PJOJCUeX5DkcXPcH0ClvPqxvSP+3pa8+uUmtpTz6QcoG8NaD6ZGaCYP3y h3SHHWfn965L0dc8bFOzdsoQoWOVzrq0ONOxyMJQreSQCnvOWbVvbztEYimxmhDBkamn NKSmAuSRzMXLgDmTGtNaVcVpdZZWEUTkv37rC9BKeR1aKvf+aPnpbCmMGi/EhkRSAQp4 tpzA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=PHSx/CGWMYUlu4wfKzSTY+tbrWqGA6GP82ZeBxk1Lzk=; b=nTBnj28YPO/GW7i+4n2QhIv+68+zJRFn9tlI+Ap9anA8QRxDn/l7z+lv+MzQQ9ZMw7 AIU+zlOxNfMFn4Q6pvLu8GDmykDSCqN5O3DQTbN/5G29RfWl1ZJIaIEMEjE8dmcszkRq ZUTqibWkBlNdmv+ssBaY12r4reAakye5XyTaDQN29FQAzE2tXTqf7LVl6GGZuKXrRsPN +RaZjbVTr0z7ufmhOlZbUkefuRfS90s/xXE2BP/I5ZS7qZ5cLIV8g4ovJ3q8JfHaW0sU 4A8pskzB9zfKzsR7aFf72FU5OFIWqAxqyTeUObd0uPMYaiWd0SdQAvp7jpz8KiO2yng7 6PYQ== X-Gm-Message-State: AOAM533zOZlHvtbskNoul6OH78Bj+vX6ryznzulNu4KWrB44t4QUiPav PkcX1mNHXUGk10TXGSVz4sHxwA== X-Google-Smtp-Source: ABdhPJxuIeR2m4zNxfUyYASFYOKIh8/CDI0v7ZJC7WkpdaLt1APzLOJJGd+g+c1MY0JYa5bD9EkHBQ== X-Received: by 2002:a1c:7c0a:0:b0:389:8d53:260e with SMTP id x10-20020a1c7c0a000000b003898d53260emr857663wmc.69.1646772608200; Tue, 08 Mar 2022 12:50:08 -0800 (PST) Received: from linaro.org ([2a00:23c5:6809:2201:546d:7d59:1703:bf96]) by smtp.gmail.com with ESMTPSA id p26-20020a1c741a000000b00389ab9a53c8sm3245758wmc.36.2022.03.08.12.50.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Mar 2022 12:50:07 -0800 (PST) From: Mike Leach To: suzuki.poulose@arm.com, coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: mathieu.poirier@linaro.org, peterz@infradead.org, mingo@redhat.com, acme@kernel.org, linux-perf-users@vger.kernel.org, leo.yan@linaro.org, Mike Leach Subject: [PATCH 04/10] coresight: etm4x: Use trace ID API to dynamically allocate trace ID Date: Tue, 8 Mar 2022 20:49:54 +0000 Message-Id: <20220308205000.27646-5-mike.leach@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220308205000.27646-1-mike.leach@linaro.org> References: <20220308205000.27646-1-mike.leach@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220308_125010_146797_BA503347 X-CRM114-Status: GOOD ( 26.02 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The trace ID API is now used to allocate trace IDs for ETM4.x / ETE devices. For perf sessions, these will be allocated on enable, and released on disable. For sysfs sessions, these will be allocated on enable, but only released on reset. This allows the sysfs session to interrogate the Trace ID used after the session is over - maintaining functional consistency with the previous allocation scheme. The trace ID will also be allocated on read of the mgmt/trctraceid file. This ensures that if perf or sysfs read this before enabling trace, the value will be the one used for the trace session. Trace ID initialisation is removed from the _probe() function. Signed-off-by: Mike Leach --- .../coresight/coresight-etm4x-core.c | 63 +++++++++++++++++-- .../coresight/coresight-etm4x-sysfs.c | 32 +++++++++- drivers/hwtracing/coresight/coresight-etm4x.h | 3 + 3 files changed, 89 insertions(+), 9 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index 7f416a12000e..aa7ea5ad8b06 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -42,6 +42,7 @@ #include "coresight-etm4x-cfg.h" #include "coresight-self-hosted-trace.h" #include "coresight-syscfg.h" +#include "coresight-trace-id.h" static int boot_enable; module_param(boot_enable, int, 0444); @@ -234,6 +235,36 @@ static int etm4_trace_id(struct coresight_device *csdev) return drvdata->trcid; } +int etm4_read_alloc_trace_id(struct etmv4_drvdata *drvdata) +{ + int trace_id; + + /* + * This will allocate a trace ID to the cpu, + * or return the one currently allocated. + */ + trace_id = coresight_trace_id_get_cpu_id(drvdata->cpu, + coresight_get_trace_id_map()); + if (trace_id > 0) { + spin_lock(&drvdata->spinlock); + drvdata->trcid = (u8)trace_id; + spin_unlock(&drvdata->spinlock); + } else { + pr_err("Failed to allocate trace ID for %s on CPU%d\n", + dev_name(&drvdata->csdev->dev), drvdata->cpu); + } + return trace_id; +} + +void etm4_release_trace_id(struct etmv4_drvdata *drvdata) +{ + coresight_trace_id_put_cpu_id(drvdata->cpu, + coresight_get_trace_id_map()); + spin_lock(&drvdata->spinlock); + drvdata->trcid = 0; + spin_unlock(&drvdata->spinlock); +} + struct etm4_enable_arg { struct etmv4_drvdata *drvdata; int rc; @@ -717,9 +748,18 @@ static int etm4_enable_perf(struct coresight_device *csdev, ret = etm4_parse_event_config(csdev, event); if (ret) goto out; + + /* allocate a trace ID */ + ret = etm4_read_alloc_trace_id(drvdata); + if (ret < 0) + goto out; + /* And enable it */ ret = etm4_enable_hw(drvdata); + /* failed to enable */ + if (ret) + etm4_release_trace_id(drvdata); out: return ret; } @@ -739,6 +779,11 @@ static int etm4_enable_sysfs(struct coresight_device *csdev) return ret; } + /* allocate a trace ID */ + ret = etm4_read_alloc_trace_id(drvdata); + if (ret < 0) + return ret; + spin_lock(&drvdata->spinlock); /* @@ -756,6 +801,8 @@ static int etm4_enable_sysfs(struct coresight_device *csdev) if (!ret) dev_dbg(&csdev->dev, "ETM tracing enabled\n"); + else + etm4_release_trace_id(drvdata); return ret; } @@ -883,6 +930,9 @@ static int etm4_disable_perf(struct coresight_device *csdev, /* TRCVICTLR::SSSTATUS, bit[9] */ filters->ssstatus = (control & BIT(9)); + /* release trace ID - this may pend release if perf session is still active */ + etm4_release_trace_id(drvdata); + return 0; } @@ -908,6 +958,13 @@ static void etm4_disable_sysfs(struct coresight_device *csdev) spin_unlock(&drvdata->spinlock); cpus_read_unlock(); + /* + * unlike for perf session - we only release trace IDs when resetting + * sysfs. This permits sysfs users to read the trace ID after the trace + * session has completed. This maintains operational behaviour with + * prior trace id allocation method + */ + dev_dbg(&csdev->dev, "ETM tracing disabled\n"); } @@ -1596,11 +1653,6 @@ static int etm4_dying_cpu(unsigned int cpu) return 0; } -static void etm4_init_trace_id(struct etmv4_drvdata *drvdata) -{ - drvdata->trcid = coresight_get_trace_id(drvdata->cpu); -} - static int __etm4_cpu_save(struct etmv4_drvdata *drvdata) { int i, ret = 0; @@ -2005,7 +2057,6 @@ static int etm4_probe(struct device *dev, void __iomem *base, u32 etm_pid) if (!desc.name) return -ENOMEM; - etm4_init_trace_id(drvdata); etm4_set_default(&drvdata->config); pdata = coresight_get_platform_data(dev); diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c index 21687cc1e4e2..bb69a203b833 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c @@ -266,10 +266,11 @@ static ssize_t reset_store(struct device *dev, config->vmid_mask0 = 0x0; config->vmid_mask1 = 0x0; - drvdata->trcid = drvdata->cpu + 1; - spin_unlock(&drvdata->spinlock); + /* for sysfs - only release trace id when resetting */ + etm4_release_trace_id(drvdata); + cscfg_csdev_reset_feats(to_coresight_device(dev)); return size; @@ -2355,6 +2356,31 @@ static struct attribute *coresight_etmv4_attrs[] = { NULL, }; +/* + * Trace ID allocated dynamically on enable - but also allocate on read + * in case sysfs or perf read before enable to ensure consistent metadata + * information for trace decode + */ +static ssize_t trctraceid_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + int trace_id; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + trace_id = etm4_read_alloc_trace_id(drvdata); + if (trace_id < 0) + return trace_id; + + return scnprintf(buf, PAGE_SIZE, "0x%x\n", trace_id); +} + +/* mgmt group uses extended attributes - no standard macro available */ +static struct dev_ext_attribute dev_attr_trctraceid = { + __ATTR(trctraceid, 0444, trctraceid_show, NULL), + (void *)(unsigned long)TRCTRACEIDR +}; + struct etmv4_reg { struct coresight_device *csdev; u32 offset; @@ -2491,7 +2517,7 @@ static struct attribute *coresight_etmv4_mgmt_attrs[] = { coresight_etm4x_reg(trcpidr3, TRCPIDR3), coresight_etm4x_reg(trcoslsr, TRCOSLSR), coresight_etm4x_reg(trcconfig, TRCCONFIGR), - coresight_etm4x_reg(trctraceid, TRCTRACEIDR), + &dev_attr_trctraceid.attr.attr, coresight_etm4x_reg(trcdevarch, TRCDEVARCH), NULL, }; diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h index 3c4d69b096ca..64976a00c839 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -1010,4 +1010,7 @@ static inline bool etm4x_is_ete(struct etmv4_drvdata *drvdata) { return drvdata->arch >= ETM_ARCH_ETE; } + +int etm4_read_alloc_trace_id(struct etmv4_drvdata *drvdata); +void etm4_release_trace_id(struct etmv4_drvdata *drvdata); #endif