From patchwork Tue Mar 8 20:49:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mike Leach X-Patchwork-Id: 12774373 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 477D3C433F5 for ; Tue, 8 Mar 2022 20:53:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:List-Subscribe:List-Help: List-Post:List-Archive:List-Unsubscribe:List-Id:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=Q4fKxYS6elxT7QgqF29VpPyhlz2u6Rz227Ylkytm5jI=; b=s2+BlBosvukGob 6Ult3Lp3aXcf1OqZWYSDefJpVX/YSj7btLEDCKRg/ZRMjFko3jRvlbr/3OKBSL2LBio26ZtqpbkMd HcYCS0jfoRdvhrSCRLsetEfyqiSN2b9JIXjJlw85gkzGLYEnGhWjTRzAxghCFMNzJuIVSkPlorjuM FLf2DuR2NZ42ucsDbR5Ui8ogQwkAlNvDD2KCm25OFhDbePzscm/zPFem4LiL/QPykjkGOpb/isf+7 wwVcY6P5qjVyDyKa83vMadygWvOz/W403Q3g0m16ka9Y5uWr/OmgYLsFfdCxRR2rDJS9nYGcpzWoy sp4kVEtYgf0vWKx+/kiw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nRgnx-006CQG-6p; Tue, 08 Mar 2022 20:51:37 +0000 Received: from mail-wr1-x42c.google.com ([2a00:1450:4864:20::42c]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nRgmY-006Bpr-W7 for linux-arm-kernel@lists.infradead.org; Tue, 08 Mar 2022 20:50:15 +0000 Received: by mail-wr1-x42c.google.com with SMTP id r10so5333wrp.3 for ; Tue, 08 Mar 2022 12:50:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=dJy0pQDaSOg6ATnrDsu3nm+8IQXiwbkO3KaKWIh49Fg=; b=wvuMmLT+F1MWoxrCIV8vR3igpSzRRRGPxcd7SkROFQl2o4JeVO/3Bjq+ZMX6lNEnOi 0axIxIE2KuvY2zmfWOcfb/Go4f1evSnclofHZOYBoykBb1aFg67AhOh7b5ESx2QfoMSl wfYT4qdM3UOr9kgOFMzZ5dV6TdWVLzy2vsDPLWv7X0rMAeyn+lbxbvpUH3JajCRiQ45K Lg3RzEv5FMje6+YSStoY8lDgkvIVv7yzkOqh47Np87VWnkJw3m5tlmuTinUr6I4hUxOY 8ac9y+Y7YXLXRcE8c4FK+hgh27i3Ioz62BiquIOoIxgT8SQ1ZbcSjXUp4lAVv24u9/vc n4xA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=dJy0pQDaSOg6ATnrDsu3nm+8IQXiwbkO3KaKWIh49Fg=; b=hVVXbTH9pXz/+vJ5AssF2SRor5eWP9AQ+68x0XyutBRKzJX39NrDx4p6ia06ZiBEFE HwVI9YLD32wXpaLmwVbCebPCLKc2xfaN0hAlubmIjNh8763sKGpRenzfMTwqT0DuCRqo 6IjIWyQGju4rkqlcRuI2yYHtPQmn3+RTrsPrM9Hr2EuYDiNxx5xeJeda4X5mTQe2PoIu AqaVmFDxV2yIyiAOvGmmBNISVJ+YplWNfBLuHry/E+ufk6Z7wjHvzXcFRnZ4PEEnwEfW DZUMC/6kRrUn1Ix18z8GEqpk0AdDXJKTy7zxSApebVcIQ7D2Lb+nCy4tkiYTj/QTLxa1 cQfQ== X-Gm-Message-State: AOAM530t0gBRUcoAzgrLzeueViRlx24idX/jDqc9bvRzHqeg66NYMQV7 n42d1Ebjlwyj2n2oNwovZCnFng== X-Google-Smtp-Source: ABdhPJwrdYIm6NC2LtonrqL5iaAbZgZ0elUfWZnw8rLwjTiE05M4nIE0BpoE0G1LHn5PCawBIn3IxA== X-Received: by 2002:a5d:5850:0:b0:1f0:2d5b:dc35 with SMTP id i16-20020a5d5850000000b001f02d5bdc35mr13445051wrf.344.1646772609794; Tue, 08 Mar 2022 12:50:09 -0800 (PST) Received: from linaro.org ([2a00:23c5:6809:2201:546d:7d59:1703:bf96]) by smtp.gmail.com with ESMTPSA id p26-20020a1c741a000000b00389ab9a53c8sm3245758wmc.36.2022.03.08.12.50.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Mar 2022 12:50:09 -0800 (PST) From: Mike Leach To: suzuki.poulose@arm.com, coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: mathieu.poirier@linaro.org, peterz@infradead.org, mingo@redhat.com, acme@kernel.org, linux-perf-users@vger.kernel.org, leo.yan@linaro.org, Mike Leach Subject: [PATCH 06/10] coresight: perf: traceid: Add perf notifiers for trace ID Date: Tue, 8 Mar 2022 20:49:56 +0000 Message-Id: <20220308205000.27646-7-mike.leach@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220308205000.27646-1-mike.leach@linaro.org> References: <20220308205000.27646-1-mike.leach@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220308_125011_110309_E96EDF45 X-CRM114-Status: GOOD ( 17.30 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Adds in notifier calls to the trace ID allocator that perf events are starting and stopping. This ensures that Trace IDs associated with CPUs remain the same throughout the perf session, and are only release when all perf sessions are complete. Signed-off-by: Mike Leach --- drivers/hwtracing/coresight/coresight-etm-perf.c | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c index c039b6ae206f..008f9dac429d 100644 --- a/drivers/hwtracing/coresight/coresight-etm-perf.c +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c @@ -22,6 +22,7 @@ #include "coresight-etm-perf.h" #include "coresight-priv.h" #include "coresight-syscfg.h" +#include "coresight-trace-id.h" static struct pmu etm_pmu; static bool etm_perf_up; @@ -223,11 +224,21 @@ static void free_event_data(struct work_struct *work) struct list_head **ppath; ppath = etm_event_cpu_path_ptr(event_data, cpu); - if (!(IS_ERR_OR_NULL(*ppath))) + if (!(IS_ERR_OR_NULL(*ppath))) { coresight_release_path(*ppath); + /* + * perf may have read a trace id for a cpu, but never actually + * executed code on that cpu - which means the trace id would + * not release on disable. Re-release here to be sure. + */ + coresight_trace_id_put_cpu_id(cpu, coresight_get_trace_id_map()); + } *ppath = NULL; } + /* mark perf event as done for trace id allocator */ + coresight_trace_id_perf_stop(); + free_percpu(event_data->path); kfree(event_data); } @@ -314,6 +325,9 @@ static void *etm_setup_aux(struct perf_event *event, void **pages, sink = user_sink = coresight_get_sink_by_id(id); } + /* tell the trace ID allocator that a perf event is starting up */ + coresight_trace_id_perf_start(); + /* check if user wants a coresight configuration selected */ cfg_hash = (u32)((event->attr.config2 & GENMASK_ULL(63, 32)) >> 32); if (cfg_hash) {