| Message ID | 20220318095417.2016-2-jianjun.wang@mediatek.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | phy: mediatek: Add PCIe PHY driver | expand |
Il 18/03/22 10:54, Jianjun Wang ha scritto: > Add YAML schema documentation for PCIe PHY on MediaTek chipsets. > > Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> > --- > .../bindings/phy/mediatek,pcie-phy.yaml | 75 +++++++++++++++++++ > 1 file changed, 75 insertions(+) > create mode 100644 Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml > > diff --git a/Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml b/Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml > new file mode 100644 > index 000000000000..868bf976568b > --- /dev/null > +++ b/Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml > @@ -0,0 +1,75 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/phy/mediatek,pcie-phy.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: MediaTek PCIe PHY > + > +maintainers: > + - Jianjun Wang <jianjun.wang@mediatek.com> > + > +description: | > + The PCIe PHY supports physical layer functionality for PCIe Gen3 port. > + > +properties: > + compatible: > + const: mediatek,mt8195-pcie-phy Since I don't expect this driver to be only for MT8195, but to be extended to support some more future MediaTek SoCs and, depending on the number of differences in the possible future Gen4 PHYs, even different gen's, I propose to add a generic compatible as const. So you'll have something like: - enum: - mediatek,mt8195-pcie-phy - const: mediatek,pcie-gen3-phy > + > + reg: > + maxItems: 1 > + ..snip.. > + > +additionalProperties: false > + > +examples: > + - | > + phy@11e80000 { > + compatible = "mediatek,mt8195-pcie-phy"; ... which would reflect here as compatible = "mediatek,mt8195-pcie-phy", "mediatek,pcie-gen3-phy" > + #phy-cells = <0>; > + reg = <0x11e80000 0x10000>; > + reg-names = "sif"; > + nvmem-cells = <&pciephy_glb_intr>, > + <&pciephy_tx_ln0_pmos>, > + <&pciephy_tx_ln0_nmos>, > + <&pciephy_rx_ln0>, > + <&pciephy_tx_ln1_pmos>, > + <&pciephy_tx_ln1_nmos>, > + <&pciephy_rx_ln1>; > + nvmem-cell-names = "glb_intr", "tx_ln0_pmos", > + "tx_ln0_nmos", "rx_ln0", > + "tx_ln1_pmos", "tx_ln1_nmos", > + "rx_ln1"; > + power-domains = <&spm 2>; > + }; Regards, Angelo
On 18/03/2022 12:12, AngeloGioacchino Del Regno wrote: > Il 18/03/22 10:54, Jianjun Wang ha scritto: >> Add YAML schema documentation for PCIe PHY on MediaTek chipsets. >> >> Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> >> --- >> .../bindings/phy/mediatek,pcie-phy.yaml | 75 +++++++++++++++++++ >> 1 file changed, 75 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml >> >> diff --git a/Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml b/Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml >> new file mode 100644 >> index 000000000000..868bf976568b >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml >> @@ -0,0 +1,75 @@ >> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/phy/mediatek,pcie-phy.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: MediaTek PCIe PHY >> + >> +maintainers: >> + - Jianjun Wang <jianjun.wang@mediatek.com> >> + >> +description: | >> + The PCIe PHY supports physical layer functionality for PCIe Gen3 port. >> + >> +properties: >> + compatible: >> + const: mediatek,mt8195-pcie-phy > > Since I don't expect this driver to be only for MT8195, but to be extended to > support some more future MediaTek SoCs and, depending on the number of differences > in the possible future Gen4 PHYs, even different gen's, I propose to add a generic > compatible as const. > > So you'll have something like: > > - enum: > - mediatek,mt8195-pcie-phy > - const: mediatek,pcie-gen3-phy I am not sure if this is a good idea. How sure are you that there will be no different PCIe Gen3 PHY not compatible with this one? Best regards, Krzysztof
On 18/03/2022 10:54, Jianjun Wang wrote: > Add YAML schema documentation for PCIe PHY on MediaTek chipsets. > > Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> > --- > .../bindings/phy/mediatek,pcie-phy.yaml | 75 +++++++++++++++++++ > 1 file changed, 75 insertions(+) > create mode 100644 Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml > > diff --git a/Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml b/Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml > new file mode 100644 > index 000000000000..868bf976568b > --- /dev/null > +++ b/Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml > @@ -0,0 +1,75 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/phy/mediatek,pcie-phy.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: MediaTek PCIe PHY > + > +maintainers: > + - Jianjun Wang <jianjun.wang@mediatek.com> > + > +description: | > + The PCIe PHY supports physical layer functionality for PCIe Gen3 port. > + > +properties: > + compatible: > + const: mediatek,mt8195-pcie-phy > + > + reg: > + maxItems: 1 > + > + reg-names: > + items: > + - const: sif > + > + "#phy-cells": > + const: 0 > + > + nvmem-cells: > + description: > + Phandles to nvmem cell that contains the efuse data, if unspecified, > + default value is used. maxItems: 7 Best regards, Krzysztof
Il 18/03/22 14:51, Krzysztof Kozlowski ha scritto: > On 18/03/2022 12:12, AngeloGioacchino Del Regno wrote: >> Il 18/03/22 10:54, Jianjun Wang ha scritto: >>> Add YAML schema documentation for PCIe PHY on MediaTek chipsets. >>> >>> Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> >>> --- >>> .../bindings/phy/mediatek,pcie-phy.yaml | 75 +++++++++++++++++++ >>> 1 file changed, 75 insertions(+) >>> create mode 100644 Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml >>> >>> diff --git a/Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml b/Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml >>> new file mode 100644 >>> index 000000000000..868bf976568b >>> --- /dev/null >>> +++ b/Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml >>> @@ -0,0 +1,75 @@ >>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) >>> +%YAML 1.2 >>> +--- >>> +$id: http://devicetree.org/schemas/phy/mediatek,pcie-phy.yaml# >>> +$schema: http://devicetree.org/meta-schemas/core.yaml# >>> + >>> +title: MediaTek PCIe PHY >>> + >>> +maintainers: >>> + - Jianjun Wang <jianjun.wang@mediatek.com> >>> + >>> +description: | >>> + The PCIe PHY supports physical layer functionality for PCIe Gen3 port. >>> + >>> +properties: >>> + compatible: >>> + const: mediatek,mt8195-pcie-phy >> >> Since I don't expect this driver to be only for MT8195, but to be extended to >> support some more future MediaTek SoCs and, depending on the number of differences >> in the possible future Gen4 PHYs, even different gen's, I propose to add a generic >> compatible as const. >> >> So you'll have something like: >> >> - enum: >> - mediatek,mt8195-pcie-phy >> - const: mediatek,pcie-gen3-phy > > I am not sure if this is a good idea. How sure are you that there will > be no different PCIe Gen3 PHY not compatible with this one? > > Thanks for pointing that out, I have underestimated this option. Perhaps Jianjun may be more informed about whether my proposal is valid or not. Cheers, Angelo > Best regards, > Krzysztof
On Fri, 2022-03-18 at 14:56 +0100, AngeloGioacchino Del Regno wrote: > Il 18/03/22 14:51, Krzysztof Kozlowski ha scritto: > > On 18/03/2022 12:12, AngeloGioacchino Del Regno wrote: > > > Il 18/03/22 10:54, Jianjun Wang ha scritto: > > > > Add YAML schema documentation for PCIe PHY on MediaTek > > > > chipsets. > > > > > > > > Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> > > > > --- > > > > .../bindings/phy/mediatek,pcie-phy.yaml | 75 > > > > +++++++++++++++++++ > > > > 1 file changed, 75 insertions(+) > > > > create mode 100644 > > > > Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml > > > > > > > > diff --git > > > > a/Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml > > > > b/Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml > > > > new file mode 100644 > > > > index 000000000000..868bf976568b > > > > --- /dev/null > > > > +++ b/Documentation/devicetree/bindings/phy/mediatek,pcie- > > > > phy.yaml > > > > @@ -0,0 +1,75 @@ > > > > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > > > > +%YAML 1.2 > > > > +--- > > > > +$id: http://devicetree.org/schemas/phy/mediatek,pcie-phy.yaml# > > > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > > > + > > > > +title: MediaTek PCIe PHY > > > > + > > > > +maintainers: > > > > + - Jianjun Wang <jianjun.wang@mediatek.com> > > > > + > > > > +description: | > > > > + The PCIe PHY supports physical layer functionality for PCIe > > > > Gen3 port. > > > > + > > > > +properties: > > > > + compatible: > > > > + const: mediatek,mt8195-pcie-phy > > > > > > Since I don't expect this driver to be only for MT8195, but to be > > > extended to > > > support some more future MediaTek SoCs and, depending on the > > > number of differences > > > in the possible future Gen4 PHYs, even different gen's, I propose > > > to add a generic > > > compatible as const. > > > > > > So you'll have something like: > > > > > > - enum: > > > - mediatek,mt8195-pcie-phy > > > - const: mediatek,pcie-gen3-phy > > > > I am not sure if this is a good idea. How sure are you that there > > will > > be no different PCIe Gen3 PHY not compatible with this one? > > > > > > Thanks for pointing that out, I have underestimated this option. > > Perhaps Jianjun may be more informed about whether my proposal is > valid or not. Many thanks for the suggestions. Currently, we only have this PCIe Gen3 PHY, and I don't think we are planning other PCIe Gen3 PHYs with different software interfaces, even in the next generation, we want to make sure it has a similar interface to this generation, so I prefer to add a generic ones to support more SoCs that need this driver. Thanks. > > Cheers, > Angelo > > > Best regards, > > Krzysztof > >
Hi Krzysztof, On Fri, 2022-03-18 at 14:55 +0100, Krzysztof Kozlowski wrote: > On 18/03/2022 10:54, Jianjun Wang wrote: > > Add YAML schema documentation for PCIe PHY on MediaTek chipsets. > > > > Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> > > --- > > .../bindings/phy/mediatek,pcie-phy.yaml | 75 > > +++++++++++++++++++ > > 1 file changed, 75 insertions(+) > > create mode 100644 > > Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml > > > > diff --git a/Documentation/devicetree/bindings/phy/mediatek,pcie- > > phy.yaml b/Documentation/devicetree/bindings/phy/mediatek,pcie- > > phy.yaml > > new file mode 100644 > > index 000000000000..868bf976568b > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml > > @@ -0,0 +1,75 @@ > > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/phy/mediatek,pcie-phy.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: MediaTek PCIe PHY > > + > > +maintainers: > > + - Jianjun Wang <jianjun.wang@mediatek.com> > > + > > +description: | > > + The PCIe PHY supports physical layer functionality for PCIe Gen3 > > port. > > + > > +properties: > > + compatible: > > + const: mediatek,mt8195-pcie-phy > > + > > + reg: > > + maxItems: 1 > > + > > + reg-names: > > + items: > > + - const: sif > > + > > + "#phy-cells": > > + const: 0 > > + > > + nvmem-cells: > > + description: > > + Phandles to nvmem cell that contains the efuse data, if > > unspecified, > > + default value is used. > > maxItems: 7 Thanks for your review, I'll fix it in the next version. > > Best regards, > Krzysztof
On Fri, Mar 18, 2022 at 9:56 PM AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> wrote: > > Il 18/03/22 14:51, Krzysztof Kozlowski ha scritto: > > On 18/03/2022 12:12, AngeloGioacchino Del Regno wrote: > >> Il 18/03/22 10:54, Jianjun Wang ha scritto: > >>> Add YAML schema documentation for PCIe PHY on MediaTek chipsets. > >>> > >>> Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> > >>> --- > >>> .../bindings/phy/mediatek,pcie-phy.yaml | 75 +++++++++++++++++++ > >>> 1 file changed, 75 insertions(+) > >>> create mode 100644 Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml > >>> > >>> diff --git a/Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml b/Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml > >>> new file mode 100644 > >>> index 000000000000..868bf976568b > >>> --- /dev/null > >>> +++ b/Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml > >>> @@ -0,0 +1,75 @@ > >>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > >>> +%YAML 1.2 > >>> +--- > >>> +$id: http://devicetree.org/schemas/phy/mediatek,pcie-phy.yaml# > >>> +$schema: http://devicetree.org/meta-schemas/core.yaml# > >>> + > >>> +title: MediaTek PCIe PHY > >>> + > >>> +maintainers: > >>> + - Jianjun Wang <jianjun.wang@mediatek.com> > >>> + > >>> +description: | > >>> + The PCIe PHY supports physical layer functionality for PCIe Gen3 port. > >>> + > >>> +properties: > >>> + compatible: > >>> + const: mediatek,mt8195-pcie-phy > >> > >> Since I don't expect this driver to be only for MT8195, but to be extended to > >> support some more future MediaTek SoCs and, depending on the number of differences > >> in the possible future Gen4 PHYs, even different gen's, I propose to add a generic > >> compatible as const. > >> > >> So you'll have something like: > >> > >> - enum: > >> - mediatek,mt8195-pcie-phy > >> - const: mediatek,pcie-gen3-phy > > > > I am not sure if this is a good idea. How sure are you that there will > > be no different PCIe Gen3 PHY not compatible with this one? > > > > > > Thanks for pointing that out, I have underestimated this option. > > Perhaps Jianjun may be more informed about whether my proposal is valid or not. Just FYI, for Allwinner and I believe Rockchip as well, the compatible strings always list the first SoC the hardware block was seen on known at the time of driver/binding submission. No generic compatible strings are ever used. Not sure if that's the general rule or not. ChenYu
diff --git a/Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml b/Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml new file mode 100644 index 000000000000..868bf976568b --- /dev/null +++ b/Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml @@ -0,0 +1,75 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/mediatek,pcie-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek PCIe PHY + +maintainers: + - Jianjun Wang <jianjun.wang@mediatek.com> + +description: | + The PCIe PHY supports physical layer functionality for PCIe Gen3 port. + +properties: + compatible: + const: mediatek,mt8195-pcie-phy + + reg: + maxItems: 1 + + reg-names: + items: + - const: sif + + "#phy-cells": + const: 0 + + nvmem-cells: + description: + Phandles to nvmem cell that contains the efuse data, if unspecified, + default value is used. + + nvmem-cell-names: + items: + - const: glb_intr + - const: tx_ln0_pmos + - const: tx_ln0_nmos + - const: rx_ln0 + - const: tx_ln1_pmos + - const: tx_ln1_nmos + - const: rx_ln1 + + power-domains: + maxItems: 1 + +required: + - compatible + - reg + - reg-names + - "#phy-cells" + - power-domains + +additionalProperties: false + +examples: + - | + phy@11e80000 { + compatible = "mediatek,mt8195-pcie-phy"; + #phy-cells = <0>; + reg = <0x11e80000 0x10000>; + reg-names = "sif"; + nvmem-cells = <&pciephy_glb_intr>, + <&pciephy_tx_ln0_pmos>, + <&pciephy_tx_ln0_nmos>, + <&pciephy_rx_ln0>, + <&pciephy_tx_ln1_pmos>, + <&pciephy_tx_ln1_nmos>, + <&pciephy_rx_ln1>; + nvmem-cell-names = "glb_intr", "tx_ln0_pmos", + "tx_ln0_nmos", "rx_ln0", + "tx_ln1_pmos", "tx_ln1_nmos", + "rx_ln1"; + power-domains = <&spm 2>; + };
Add YAML schema documentation for PCIe PHY on MediaTek chipsets. Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> --- .../bindings/phy/mediatek,pcie-phy.yaml | 75 +++++++++++++++++++ 1 file changed, 75 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml