| Message ID | 20220318195913.17459-4-alisaidi@amazon.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | perf: arm-spe: Decode SPE source and use for perf c2c | expand |
diff --git a/tools/perf/util/mem-events.c b/tools/perf/util/mem-events.c index e5e405185498..084977cfebef 100644 --- a/tools/perf/util/mem-events.c +++ b/tools/perf/util/mem-events.c @@ -539,6 +539,15 @@ do { \ stats->ld_llchit++; } + /* + * A hit in another cores cache must mean a llc snoop + * filter hit + */ + if (lnum == P(LVLNUM, ANY_CACHE)) { + if (snoop & P(SNOOP, HITM)) + HITM_INC(lcl_hitm); + } + if (lvl & P(LVL, LOC_RAM) || lnum == P(LVLNUM, RAM)) { stats->lcl_dram++; if (snoop & P(SNOOP, HIT))
For loads that hit in a the LLC snoop filter and are fulfilled from a higher level cache on arm64 Neoverse cores, it's not usually clear what the true level of the cache the data came from (i.e. a transfer from a core could come from it's L1 or L2). Instead of making an assumption of where the line came from, add support for incrementing HITM if the source is CACHE_ANY. Since other architectures don't seem to populate the mem_lvl_num field here there shouldn't be a change in functionality. Signed-off-by: Ali Saidi <alisaidi@amazon.com> --- tools/perf/util/mem-events.c | 9 +++++++++ 1 file changed, 9 insertions(+)