diff mbox series

[v1,10/10] arm64: dts: imx8mm-verdin: add sd1 sleep pinctrl

Message ID 20220324155649.285924-11-marcel@ziswiler.com (mailing list archive)
State New, archived
Headers show
Series arm64: dts: imx8mm-verdin: minor updates | expand

Commit Message

Marcel Ziswiler March 24, 2022, 3:56 p.m. UTC 
From: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Add SD1 sleep pinctrl to avoid backfeeding during sleep.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
---

 .../boot/dts/freescale/imx8mm-verdin.dtsi     | 20 ++++++++++++++++++-
 1 file changed, 19 insertions(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
index 97dd7a00d63b..eafa88d980b3 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
@@ -757,10 +757,11 @@  &usdhc2 {
 	bus-width = <4>;
 	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
 	disable-wp;
-	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
 	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_cd>;
 	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_cd>;
 	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>;
+	pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_cd_sleep>;
 	vmmc-supply = <&reg_usdhc2_vmmc>;
 };
 
@@ -1174,6 +1175,11 @@  pinctrl_usdhc2_cd: usdhc2cdgrp {
 			<MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12		0x6>;	/* SODIMM 84 */
 	};
 
+	pinctrl_usdhc2_cd_sleep: usdhc2cdslpgrp {
+		fsl,pins =
+			<MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12		0x0>;	/* SODIMM 84 */
+	};
+
 	pinctrl_usdhc2_pwr_en: usdhc2pwrengrp {
 		fsl,pins =
 			<MX8MM_IOMUXC_NAND_CLE_GPIO3_IO5		0x6>;	/* SODIMM 76 */
@@ -1216,6 +1222,18 @@  pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
 			<MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x96>;
 	};
 
+	/* Avoid backfeeding with removed card power */
+	pinctrl_usdhc2_sleep: usdhc2slpgrp {
+		fsl,pins =
+			<MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0x0>,
+			<MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x0>,
+			<MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x0>,
+			<MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x0>,
+			<MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x0>,
+			<MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x0>,
+			<MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x0>;
+	};
+
 	/*
 	 * On-module Wi-Fi/BT or type specific SDHC interface
 	 * (e.g. on X52 extension slot of Verdin Development Board)