From patchwork Sun Mar 27 20:03:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabien Parent X-Patchwork-Id: 12792902 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A3AC4C433FE for ; Sun, 27 Mar 2022 20:05:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=xLOunt0MMGY+y5ddu5wOBcC8D79KcfmHbcRuagoaya8=; b=DPAoXMRUteSwtR OBn6xVw1pDT6T+q9W8Rxknd3rYVd++LzDf1Zdln2xK1y0FBDL0uoAXTpyAopillVEg6gGi5fiTrMj tENmuD6KzIp66ZP6Z5NfwUQwegkj04SERl+pFYRepu+6LlLvE9eckv6ueCk6izJHzFsdRXDED4VA8 wlAUJLjMXzGohTf91iFZhg4sljtYREFgFeUUMICD26lPFOd+dBziMzbjN7HbK3u9XXPeXcc2jg9go /O5roTSkOYq2yeJA+XmnKOcofOfc4MnIb7TsB1lTqj3IYXgfOyfWmat5lX9dpbcVBdvFYSpJHud0L bRw79uFmifIDWbuRSBNg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nYZ7X-006AD6-Fy; Sun, 27 Mar 2022 20:04:15 +0000 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nYZ7I-006A5z-0X for linux-arm-kernel@lists.infradead.org; Sun, 27 Mar 2022 20:04:02 +0000 Received: by mail-wm1-x32f.google.com with SMTP id i204-20020a1c3bd5000000b0038ce25c870dso47707wma.1 for ; Sun, 27 Mar 2022 13:03:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=LOpeigcZgHASXsFgMMBDoubFgh2CN2uJnv1/KTETRuA=; b=a9ttLlc8J+QluSbyoogIjxVh3kkfhmSV2iRD9KjvzmYA8cI5sArRfkAnuZ4Mgy8Fkl c8xd7HGGciOE9RzV8EUHcmFsGg8pA2SK/7cnOlISrQ4z/42cjb9ZyLN09lDBQ8qo2gLp Ul5451wsdPvpag7QK1qaBGq/dP/48bBu5RSAZYsBh3ZLZM53G/yswXFDcA4U3UzzOFor nrB+apUN9ahlGV7KzR6zQYlgl0UWMBugUF1UqV+OZvsZ8wCH36feCtLTXUyX69KCle3U dJHnCW2yqZsnvGEzrVJrB3ggrbE55AEyxzYOHv1lzhIHGipRFVKwAh9atRy9cNT8kcun SNBQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=LOpeigcZgHASXsFgMMBDoubFgh2CN2uJnv1/KTETRuA=; b=TeTLJJiFUq22RyHrxiOkEPbAbrxgwKlVIhIkWVWjjjd/aSNMzAtT5rHGx8t/6m1YDe e45I80JBiRB/lo++xkQSJLbTT3Hh1jthdB2dY03WkLGL+8oCsMJxBazI4I5zRoDAH1eR /qYTeivH47eObCuc7408caKpgMAotqHTRuFJ9TsKvfyNj1Yb5kZcNhyLH98t5UH/AA3f CkVnqAiN0VbvqyTLnCBm45a8dAqangyEj7byWCWGMFahDAQ4+1sgfXPBLSuYTB3/MgRS Q8lbeivsJIyV+feE4QHs88CyPM+/XOxK5rvx8M59GNRKdOry2AP8JfttTByRtd92q4m8 Mr5Q== X-Gm-Message-State: AOAM533vrdgpUEJPyQyPdpgD/VpnRH2XXRznL3TuAK7jbh/f6EjYkoXN EfnzWWYT48Zk7sb0naeSJ3spFA== X-Google-Smtp-Source: ABdhPJzj03dLfQxdM3Tk+fIS05qCASk4bGj0nPKTvbNPXGhQXceEm9qL53zGhQPGzaiUQRlvI+Tsbg== X-Received: by 2002:a05:600c:3547:b0:38c:ac1c:53e9 with SMTP id i7-20020a05600c354700b0038cac1c53e9mr21299240wmq.159.1648411438180; Sun, 27 Mar 2022 13:03:58 -0700 (PDT) Received: from localhost.localdomain ([88.160.162.107]) by smtp.gmail.com with ESMTPSA id f14-20020a05600c154e00b0038d06cc21b2sm1354555wmg.35.2022.03.27.13.03.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Mar 2022 13:03:57 -0700 (PDT) From: Fabien Parent To: Matthias Brugger , Rob Herring , Krzysztof Kozlowski Cc: Fabien Parent , linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 2/4] arm64: dts: mediatek: Add device-tree for MT8195 Demo board Date: Sun, 27 Mar 2022 22:03:10 +0200 Message-Id: <20220327200312.3090515-3-fparent@baylibre.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220327200312.3090515-1-fparent@baylibre.com> References: <20220327200312.3090515-1-fparent@baylibre.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220327_130400_167500_DEEAF8C5 X-CRM114-Status: GOOD ( 18.22 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add basic device-tree for the MT8195 Demo board. The Demo board is made by MediaTek and has a MT8195 SoC, associated with the MT6359 and MT6360 PMICs, and the MT7921 connectivity chip. The IOs available on that board are: * 1 USB Type-C connector with DP aux mode support * 1 USB Type-A connector * 1 full size HDMI RX and 1 full size HDMI TX connector * 1 uSD slot * 40 pins header * SPI interface header * 1 M.2 slot * 1 audio jack * 1 micro-USB port for serial debug * 2 connectors for DSI displays * 3 connectors for CSI cameras * 1 connector for a eDP panel * 1 MMC storage This commit adds basic support in order to be able to boot. Signed-off-by: Fabien Parent Tested-by: Mattijs Korpershoek --- v2: * remove empty i2c nodes * remove empty spi node * remove unused pcie pinctrls * fixup node nodes to not contains underscore * rename mt6360 pmic node * move mmc1 node right after mmc0 node * use generic node name for gpio-keys * uniformize pinctrl node names arch/arm64/boot/dts/mediatek/Makefile | 1 + arch/arm64/boot/dts/mediatek/mt8195-demo.dts | 447 +++++++++++++++++++ 2 files changed, 448 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt8195-demo.dts diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile index 5da29e7223e4..c7d4636a2cb7 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -38,5 +38,6 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku0.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku176.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-pumpkin.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-evb.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-demo.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8516-pumpkin.dtb diff --git a/arch/arm64/boot/dts/mediatek/mt8195-demo.dts b/arch/arm64/boot/dts/mediatek/mt8195-demo.dts new file mode 100644 index 000000000000..d94b4e01159a --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8195-demo.dts @@ -0,0 +1,447 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2022 BayLibre, SAS. + * Author: Fabien Parent + */ +/dts-v1/; + +#include "mt8195.dtsi" +#include "mt6359.dtsi" + +#include +#include +#include +#include + +/ { + model = "MediaTek MT8195 demo board"; + compatible = "mediatek,mt8195-demo", "mediatek,mt8195"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:921600n8"; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x80000000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* 12 MiB reserved for OP-TEE (BL32) + * +-----------------------+ 0x43e0_0000 + * | SHMEM 2MiB | + * +-----------------------+ 0x43c0_0000 + * | | TA_RAM 8MiB | + * + TZDRAM +--------------+ 0x4340_0000 + * | | TEE_RAM 2MiB | + * +-----------------------+ 0x4320_0000 + */ + optee_reserved: optee@43200000 { + no-map; + reg = <0 0x43200000 0 0x00c00000>; + }; + + /* 192 KiB reserved for ARM Trusted Firmware (BL31) */ + bl31_secmon_reserved: secmon@54600000 { + no-map; + reg = <0 0x54600000 0x0 0x30000>; + }; + }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + input-name = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys_pins>; + + key-0 { + gpios = <&pio 106 GPIO_ACTIVE_LOW>; + label = "volume_up"; + linux,code = ; + wakeup-source; + debounce-interval = <15>; + }; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + status = "okay"; +}; + +&mmc0 { + status = "okay"; + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc0_default_pins>; + pinctrl-1 = <&mmc0_uhs_pins>; + bus-width = <8>; + max-frequency = <200000000>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + cap-mmc-hw-reset; + no-sdio; + no-sd; + hs400-ds-delay = <0x14c11>; + vmmc-supply = <&mt6359_vemc_1_ldo_reg>; + vqmmc-supply = <&mt6359_vufs_ldo_reg>; + non-removable; +}; + +&mmc1 { + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc1_default_pins>; + pinctrl-1 = <&mmc1_uhs_pins>; + cd-gpios = <&pio 129 GPIO_ACTIVE_LOW>; + bus-width = <4>; + max-frequency = <200000000>; + cap-sd-highspeed; + sd-uhs-sdr50; + sd-uhs-sdr104; + vmmc-supply = <&mt6360_ldo5>; + vqmmc-supply = <&mt6360_ldo3>; + status = "okay"; +}; + +&pmic { + interrupt-parent = <&pio>; + interrupts = <222 IRQ_TYPE_LEVEL_HIGH>; +}; + +&i2c6 { + clock-frequency = <400000>; + pinctrl-0 = <&i2c6_pins>; + pinctrl-names = "default"; + status = "okay"; + + mt6360: pmic@34 { + compatible = "mediatek,mt6360"; + reg = <0x34>; + interrupt-controller; + interrupt-parent = <&pio>; + interrupts = <101 IRQ_TYPE_EDGE_FALLING>; + interrupt-names = "IRQB"; + + charger { + compatible = "mediatek,mt6360-chg"; + richtek,vinovp-microvolt = <14500000>; + + otg_vbus_regulator: usb-otg-vbus-regulator { + regulator-compatible = "usb-otg-vbus"; + regulator-name = "usb-otg-vbus"; + regulator-min-microvolt = <4425000>; + regulator-max-microvolt = <5825000>; + }; + }; + + regulator { + compatible = "mediatek,mt6360-regulator"; + LDO_VIN3-supply = <&mt6360_buck2>; + + mt6360_buck1: buck1 { + regulator-compatible = "BUCK1"; + regulator-name = "mt6360,buck1"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1300000>; + regulator-allowed-modes = ; + regulator-always-on; + }; + + mt6360_buck2: buck2 { + regulator-compatible = "BUCK2"; + regulator-name = "mt6360,buck2"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1300000>; + regulator-allowed-modes = ; + regulator-always-on; + }; + + mt6360_ldo1: ldo1 { + regulator-compatible = "LDO1"; + regulator-name = "mt6360,ldo1"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3600000>; + regulator-allowed-modes = ; + }; + + mt6360_ldo2: ldo2 { + regulator-compatible = "LDO2"; + regulator-name = "mt6360,ldo2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3600000>; + regulator-allowed-modes = ; + }; + + mt6360_ldo3: ldo3 { + regulator-compatible = "LDO3"; + regulator-name = "mt6360,ldo3"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3600000>; + regulator-allowed-modes = ; + }; + + mt6360_ldo5: ldo5 { + regulator-compatible = "LDO5"; + regulator-name = "mt6360,ldo5"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3600000>; + regulator-allowed-modes = ; + }; + + mt6360_ldo6: ldo6 { + regulator-compatible = "LDO6"; + regulator-name = "mt6360,ldo6"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <2100000>; + regulator-allowed-modes = ; + }; + + mt6360_ldo7: ldo7 { + regulator-compatible = "LDO7"; + regulator-name = "mt6360,ldo7"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <2100000>; + regulator-allowed-modes = ; + regulator-always-on; + }; + }; + }; +}; + +&mt6359_vgpu11_buck_reg { + regulator-always-on; +}; + +&mt6359_vsram_others_ldo_reg { + regulator-always-on; +}; + +&mt6359_vpu_buck_reg { + regulator-always-on; +}; + +&mt6359_vcore_buck_reg { + regulator-always-on; +}; + +&mt6359_vproc1_buck_reg { + regulator-always-on; +}; + +&mt6359_vproc2_buck_reg { + regulator-always-on; +}; + +&mt6359_vsram_md_ldo_reg { + regulator-always-on; +}; + +&mt6359_vbbck_ldo_reg { + regulator-always-on; +}; + +&mt6359_vrf12_ldo_reg { + regulator-always-on; +}; + +&xhci0 { + vusb33-supply = <&mt6359_vusb_ldo_reg>; + vbus-supply = <&otg_vbus_regulator>; + status = "okay"; +}; + +&xhci1 { + vusb33-supply = <&mt6359_vusb_ldo_reg>; + status = "okay"; +}; + +&xhci2 { + vusb33-supply = <&mt6359_vusb_ldo_reg>; + status = "okay"; +}; + +&xhci3 { + vusb33-supply = <&mt6359_vusb_ldo_reg>; + status = "okay"; +}; + +&u3phy0 { + status = "okay"; +}; + +&u3phy1 { + status = "okay"; +}; + +&u3phy2 { + status = "okay"; +}; + +&u3phy3 { + status = "okay"; +}; + +&pio { + mmc0_default_pins: mmc0-default-pins { + pins-cmd-dat { + pinmux = , + , + , + , + , + , + , + , + ; + input-enable; + drive-strength = ; + bias-pull-up = ; + }; + + pin-clk { + pinmux = ; + drive-strength = ; + bias-pull-down = ; + }; + + pin-rst { + pinmux = ; + drive-strength = ; + bias-pull-up = ; + }; + }; + + mmc0_uhs_pins: mmc0-uhs-pins { + pins-cmd-dat { + pinmux = , + , + , + , + , + , + , + , + ; + input-enable; + drive-strength = ; + bias-pull-up = ; + }; + + pin-clk { + pinmux = ; + drive-strength = ; + bias-pull-down = ; + }; + + pin-ds { + pinmux = ; + drive-strength = ; + bias-pull-down = ; + }; + + pins-rst { + pinmux = ; + drive-strength = ; + bias-pull-up = ; + }; + }; + + mmc1_default_pins: mmc1-default-pins { + pins-cmd-dat { + pinmux = , + , + , + , + ; + input-enable; + drive-strength = ; + bias-pull-up = ; + }; + + pins-clk { + pinmux = ; + drive-strength = ; + bias-pull-down = ; + }; + + pins-insert { + pinmux = ; + bias-pull-up; + }; + }; + + mmc1_uhs_pins: mmc1-uhs-pins { + pins-cmd-dat { + pinmux = , + , + , + , + ; + input-enable; + drive-strength = ; + bias-pull-up = ; + }; + + pins-clk { + pinmux = ; + drive-strength = ; + bias-pull-down = ; + }; + }; + + i2c6_pins: i2c6-pins { + pins { + pinmux = , + ; + bias-pull-up; + mediatek,rsel = ; + }; + }; + + gpio_keys_pins: gpio-keys-pins { + pins { + pinmux = ; + input-enable; + }; + }; + + uart0_pins: uart0-pins { + pins { + pinmux = , + ; + }; + }; + + uart1_pins: uart1-pins { + pins { + pinmux = , + ; + }; + }; +};