diff mbox series

[1/1] arm64: dts: mt8192: Add mmc device nodes

Message ID 20220401053052.2160-2-allen-kh.cheng@mediatek.com (mailing list archive)
State New, archived
Headers show
Series mt8192: Add mmc device nodes | expand

Commit Message

Allen-KH Cheng April 1, 2022, 5:30 a.m. UTC
Add mmc nodes for mt8192 SoC.

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 33 ++++++++++++++++++++++++
 1 file changed, 33 insertions(+)

Comments

AngeloGioacchino Del Regno April 4, 2022, 12:36 p.m. UTC | #1
Il 01/04/22 07:30, Allen-KH Cheng ha scritto:
> Add mmc nodes for mt8192 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> ---
>   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 33 ++++++++++++++++++++++++
>   1 file changed, 33 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index a6da7b04b9d4..23eb92057cb9 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -989,6 +989,39 @@
>   			compatible = "mediatek,mt8192-msdc";
>   			reg = <0 0x11f60000 0 0x1000>;
>   			#clock-cells = <1>;
> +			status = "disabled";
> +		};
> +

Hello!
Please explain the reason (in the commit message) why you're disabling the
mediatek,mt8192-msdc node, which was enabled before this change.

Also, introducing the mtk-sd controller at the same address as the mt8192-msdc
clock controller will produce a warning...

Thanks,
Angelo
Allen-KH Cheng April 7, 2022, 9:12 a.m. UTC | #2
Hi Angelo,
On Mon, 2022-04-04 at 14:36 +0200, AngeloGioacchino Del Regno wrote:
> Il 01/04/22 07:30, Allen-KH Cheng ha scritto:
> > Add mmc nodes for mt8192 SoC.
> > 
> > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > ---
> >   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 33
> > ++++++++++++++++++++++++
> >   1 file changed, 33 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > index a6da7b04b9d4..23eb92057cb9 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > @@ -989,6 +989,39 @@
> >   			compatible = "mediatek,mt8192-msdc";
> >   			reg = <0 0x11f60000 0 0x1000>;
> >   			#clock-cells = <1>;
> > +			status = "disabled";
> > +		};
> > +
> 
> Hello!
> Please explain the reason (in the commit message) why you're
> disabling the
> mediatek,mt8192-msdc node, which was enabled before this change.
> 
> Also, introducing the mtk-sd controller at the same address as the
> mt8192-msdc
> clock controller will produce a warning...
> 
> Thanks,
> Angelo

In mt8192.
mmc driver would directly  write/read register(11f60000) to control
clock configure.

Alos there is no other module using msdc: clock-controller.

I would remove the clock-controller entirely and explain in commit
description.

Thanks,
Allen
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index a6da7b04b9d4..23eb92057cb9 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -989,6 +989,39 @@ 
 			compatible = "mediatek,mt8192-msdc";
 			reg = <0 0x11f60000 0 0x1000>;
 			#clock-cells = <1>;
+			status = "disabled";
+		};
+
+		mmc0: mmc@11f60000 {
+			compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc";
+			reg = <0 0x11f60000 0 0x1000>, <0 0x11f50000 0 0x1000>;
+			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>,
+				 <&msdc_top CLK_MSDC_TOP_H_MST_0P>,
+				 <&msdc_top CLK_MSDC_TOP_SRC_0P>,
+				 <&msdc_top CLK_MSDC_TOP_P_CFG>,
+				 <&msdc_top CLK_MSDC_TOP_P_MSDC0>,
+				 <&msdc_top CLK_MSDC_TOP_AXI>,
+				 <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>;
+			clock-names = "source", "hclk", "source_cg", "sys_cg",
+				      "pclk_cg", "axi_cg", "ahb_cg";
+			status = "disabled";
+		};
+
+		mmc1: mmc@11f70000 {
+			compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc";
+			reg = <0 0x11f70000 0 0x1000>, <0 0x11c70000 0 0x1000>;
+			interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>,
+				 <&msdc_top CLK_MSDC_TOP_H_MST_1P>,
+				 <&msdc_top CLK_MSDC_TOP_SRC_1P>,
+				 <&msdc_top CLK_MSDC_TOP_P_CFG>,
+				 <&msdc_top CLK_MSDC_TOP_P_MSDC1>,
+				 <&msdc_top CLK_MSDC_TOP_AXI>,
+				 <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>;
+			clock-names = "source", "hclk", "source_cg", "sys_cg",
+				      "pclk_cg", "axi_cg", "ahb_cg";
+			status = "disabled";
 		};
 
 		mfgcfg: clock-controller@13fbf000 {