From patchwork Fri Apr 1 06:36:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Kroah-Hartman X-Patchwork-Id: 12797933 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B8A46C433EF for ; Fri, 1 Apr 2022 06:38:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=Wl/OJK92W0/Ah8FYcOqkVdG7aCTa+w4cOHXcULnGyJg=; b=S/UjjJ/YHixKUC Z1tgN2G0e9mv+C4lvZQoDu+DU2Sqpn2vWPUAZrKvJgizYkwNva+vemKzfKT9RsYOzCSInjb9r6XwI PerI+dnGN/yQQU5xVYjkmsPLYjk/eTGa77ulOE1sxfldqhirpo2uxIg66Ka3eU2U7V9VEJ9Cw/PQv 3YCMICQVuGVbB8MN6n8L/u23fxjwuWR5qUt8CtLEd7ITP3Ev8vj7c5GES8thm6nldDs1qAKDktPm2 fe0XklEtPMMxLu8fbBxGN7HmgPobNt02G/keyiQpxMOSHdczz50ENYF1shE4IZ+QTaolLeOTtjjCt b72VZG9HlG3+pcK1cn8g==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1naAun-004g0n-FJ; Fri, 01 Apr 2022 06:37:45 +0000 Received: from ams.source.kernel.org ([2604:1380:4601:e00::1]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1naAuk-004fzk-BS for linux-arm-kernel@lists.infradead.org; Fri, 01 Apr 2022 06:37:43 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 980CCB82373; Fri, 1 Apr 2022 06:37:40 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0EED1C340EE; Fri, 1 Apr 2022 06:37:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1648795059; bh=WU7EpVEHMoBF7heOkQxHKcFgB6rMT/Ui3Z9et+z5tV8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=0l9OATFBrpufEGJSAsikERPD60/QP/5UEshZzLkoAQRhBIvyqUAY6zv1ZP9AlumtB 5PMEiAbbBtkNPSxuwSbtEUKMdElyLI3oHFePTyiwyQiCU4RVOlocX9ONMUj4jg9kQW T69JEwHbnEEmo0IhdPfM7wJTthpZw80sDg7nRrGk= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Will Deacon , Suzuki Poulose , linux-arm-kernel@lists.infradead.org, Anshuman Khandual , Catalin Marinas , James Morse Subject: [PATCH 4.14 08/27] arm64: Add Cortex-X2 CPU part definition Date: Fri, 1 Apr 2022 08:36:18 +0200 Message-Id: <20220401063624.469866369@linuxfoundation.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220401063624.232282121@linuxfoundation.org> References: <20220401063624.232282121@linuxfoundation.org> User-Agent: quilt/0.66 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220331_233742_578302_8F3E3E14 X-CRM114-Status: GOOD ( 10.46 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Anshuman Khandual commit 72bb9dcb6c33cfac80282713c2b4f2b254cd24d1 upstream. Add the CPU Partnumbers for the new Arm designs. Cc: Will Deacon Cc: Suzuki Poulose Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual Reviewed-by: Suzuki K Poulose Link: https://lore.kernel.org/r/1642994138-25887-2-git-send-email-anshuman.khandual@arm.com Signed-off-by: Catalin Marinas Signed-off-by: James Morse Signed-off-by: Greg Kroah-Hartman --- arch/arm64/include/asm/cputype.h | 2 ++ 1 file changed, 2 insertions(+) --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -91,6 +91,7 @@ #define ARM_CPU_PART_NEOVERSE_N1 0xD0C #define ARM_CPU_PART_CORTEX_A77 0xD0D #define ARM_CPU_PART_CORTEX_A710 0xD47 +#define ARM_CPU_PART_CORTEX_X2 0xD48 #define ARM_CPU_PART_NEOVERSE_N2 0xD49 #define APM_CPU_PART_POTENZA 0x000 @@ -121,6 +122,7 @@ #define MIDR_NEOVERSE_N1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N1) #define MIDR_CORTEX_A77 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A77) #define MIDR_CORTEX_A710 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A710) +#define MIDR_CORTEX_X2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X2) #define MIDR_NEOVERSE_N2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N2) #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX) #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)