diff mbox series

[v5,3/5] arm64: dts: rockchip: add rk356x dwc3 usb3 nodes

Message ID 20220408151237.3165046-4-pgwipeout@gmail.com (mailing list archive)
State New, archived
Headers show
Series enable usb support on rk356x | expand

Commit Message

Peter Geis April 8, 2022, 3:12 p.m. UTC 
Add the dwc3 device nodes to the rk356x device trees.
The rk3566 has one usb2 capable dwc3 otg controller and one usb3 capable
dwc3 host controller.
The rk3568 has one usb3 capable dwc3 otg controller and one usb3 capable
dwc3 host controller.

Signed-off-by: Peter Geis <pgwipeout@gmail.com>
Tested-by: Frank Wunderlich <frank-w@public-files.de>
---
 arch/arm64/boot/dts/rockchip/rk3566.dtsi | 11 ++++++++
 arch/arm64/boot/dts/rockchip/rk3568.dtsi |  9 ++++++
 arch/arm64/boot/dts/rockchip/rk356x.dtsi | 35 +++++++++++++++++++++++-
 3 files changed, 54 insertions(+), 1 deletion(-)

Comments

Frank Wunderlich April 8, 2022, 4:14 p.m. UTC | #1 
Hi

seems like usb (2+3) is broken in 5.18-rc1

i see controllers, ports are powered, but no device detection.

maybe anyone else have same behaviour with different board?

regards Frank
Peter Geis April 8, 2022, 11:39 p.m. UTC | #2 
On Fri, Apr 8, 2022 at 12:14 PM Frank Wunderlich
<frank-w@public-files.de> wrote:
>
> Hi

Good Evening,

>
> seems like usb (2+3) is broken in 5.18-rc1
>
> i see controllers, ports are powered, but no device detection.
>
> maybe anyone else have same behaviour with different board?

Yes, it seems you are correct, there has been a regression with xhci
between v5.17 and v5.18.
I'm bisecting now.

>
> regards Frank

Thanks for reporting it!
Very Respectfully,
Peter Geis
Frank Wunderlich April 9, 2022, 7:23 a.m. UTC | #3 
Tested on mediatek board (mt7623/bpi-r2) and there xhci is working.
So it is no problem in core/protocol and specific to rockchip xhci driver.

at least i nailed it down to these 2 commits in drivers/usb/dwc3/core.c, without them it works

5114c3ee2487 2022-01-27 usb: dwc3: Calculate REFCLKPER based on reference clock
33fb697ec7e5 2022-01-27 usb: dwc3: Get clocks individually

regards Frank


> Gesendet: Samstag, 09. April 2022 um 01:39 Uhr
> Von: "Peter Geis" <pgwipeout@gmail.com>

> On Fri, Apr 8, 2022 at 12:14 PM Frank Wunderlich
> <frank-w@public-files.de> wrote:

> > seems like usb (2+3) is broken in 5.18-rc1
> >
> > i see controllers, ports are powered, but no device detection.
> >
> > maybe anyone else have same behaviour with different board?
>
> Yes, it seems you are correct, there has been a regression with xhci
> between v5.17 and v5.18.
> I'm bisecting now.
Frank Wunderlich April 9, 2022, 7:37 a.m. UTC | #4 
Got it,
these Patches require different clock names

ref_clk => ref
bus_clk => bus_early

after renaming usb works on my board

will send an follow-up patch for this series

regards Frank


> Gesendet: Samstag, 09. April 2022 um 09:23 Uhr
> Von: "Frank Wunderlich" <frank-w@public-files.de>
>
> at least i nailed it down to these 2 commits in drivers/usb/dwc3/core.c, without them it works
>
> 5114c3ee2487 2022-01-27 usb: dwc3: Calculate REFCLKPER based on reference clock
> 33fb697ec7e5 2022-01-27 usb: dwc3: Get clocks individually
Peter Geis April 9, 2022, 3:32 p.m. UTC | #5 
On Sat, Apr 9, 2022 at 3:37 AM Frank Wunderlich <frank-w@public-files.de> wrote:
>
> Got it,
> these Patches require different clock names
>
> ref_clk => ref
> bus_clk => bus_early
>
> after renaming usb works on my board
>
> will send an follow-up patch for this series
>
> regards Frank
>
>
> > Gesendet: Samstag, 09. April 2022 um 09:23 Uhr
> > Von: "Frank Wunderlich" <frank-w@public-files.de>
> >
> > at least i nailed it down to these 2 commits in drivers/usb/dwc3/core.c, without them it works
> >
> > 5114c3ee2487 2022-01-27 usb: dwc3: Calculate REFCLKPER based on reference clock
> > 33fb697ec7e5 2022-01-27 usb: dwc3: Get clocks individually
>

I've submitted a fix for the dwc3 issue.
https://patchwork.kernel.org/project/linux-rockchip/patch/20220409152116.3834354-1-pgwipeout@gmail.com/
The offending commit was: 33fb697ec7e5 ("usb: dwc3: Get clocks individually").
It breaks backwards compatibility with rk3328, which follows the
rockchip,dwc3.yaml dt-binding, and thus this series as well.

This fix is standalone and necessary no matter which route we decide
to go with this series (and the rk3328/rk3399 support as well).
With this patch, dwc3 is functional on the rk356x as the series was
submitted, so if we decide to fix everything all at once, that is a
viable option.

For those not following the other conversation, here is the TLDR:
- rockchip,dwc3.yaml has different clock names than snps,dwc3.yaml
- rk3328 and rk356x attach directly to the dwc3 core driver
- rk3399 uses the dwc3-simple driver, which still uses the clk_bulk api.
- commit 33fb697ec7e5 changed to individual clocks, which follow
snps,dwc3.yaml naming
- to correct this beyond my fix patch, we would need to align
rockchip,dwc3.yaml with snps,dwc3.yaml, which means rk3328, rk3399,
and rk356x will move to the snps clock naming scheme.

I think we need Rob Herring to weigh in here, as this is a rather
uncomfortable dt-binding issue.
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/rockchip/rk3566.dtsi b/arch/arm64/boot/dts/rockchip/rk3566.dtsi
index 3839eef5e4f7..0b957068ff89 100644
--- a/arch/arm64/boot/dts/rockchip/rk3566.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3566.dtsi
@@ -6,6 +6,10 @@  / {
 	compatible = "rockchip,rk3566";
 };
 
+&pipegrf {
+	compatible = "rockchip,rk3566-pipe-grf", "syscon";
+};
+
 &power {
 	power-domain@RK3568_PD_PIPE {
 		reg = <RK3568_PD_PIPE>;
@@ -18,3 +22,10 @@  power-domain@RK3568_PD_PIPE {
 		#power-domain-cells = <0>;
 	};
 };
+
+&usb_host0_xhci {
+	phys = <&usb2phy0_otg>;
+	phy-names = "usb2-phy";
+	extcon = <&usb2phy0>;
+	maximum-speed = "high-speed";
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
index 5b0f528d6818..8ba9334f9753 100644
--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
@@ -99,6 +99,10 @@  opp-1992000000 {
 	};
 };
 
+&pipegrf {
+	compatible = "rockchip,rk3568-pipe-grf", "syscon";
+};
+
 &power {
 	power-domain@RK3568_PD_PIPE {
 		reg = <RK3568_PD_PIPE>;
@@ -114,3 +118,8 @@  power-domain@RK3568_PD_PIPE {
 		#power-domain-cells = <0>;
 	};
 };
+
+&usb_host0_xhci {
+	phys = <&usb2phy0_otg>, <&combphy0 PHY_TYPE_USB3>;
+	phy-names = "usb2-phy", "usb3-phy";
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
index 7cdef800cb3c..ca20d7b91fe5 100644
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
@@ -230,6 +230,40 @@  scmi_shmem: sram@0 {
 		};
 	};
 
+	usb_host0_xhci: usb@fcc00000 {
+		compatible = "rockchip,rk3568-dwc3", "snps,dwc3";
+		reg = <0x0 0xfcc00000 0x0 0x400000>;
+		interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru CLK_USB3OTG0_REF>, <&cru CLK_USB3OTG0_SUSPEND>,
+			 <&cru ACLK_USB3OTG0>;
+		clock-names = "ref_clk", "suspend_clk",
+			      "bus_clk";
+		dr_mode = "host";
+		phy_type = "utmi_wide";
+		power-domains = <&power RK3568_PD_PIPE>;
+		resets = <&cru SRST_USB3OTG0>;
+		snps,dis_u2_susphy_quirk;
+		status = "disabled";
+	};
+
+	usb_host1_xhci: usb@fd000000 {
+		compatible = "rockchip,rk3568-dwc3", "snps,dwc3";
+		reg = <0x0 0xfd000000 0x0 0x400000>;
+		interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru CLK_USB3OTG1_REF>, <&cru CLK_USB3OTG1_SUSPEND>,
+			 <&cru ACLK_USB3OTG1>;
+		clock-names = "ref_clk", "suspend_clk",
+			      "bus_clk";
+		dr_mode = "host";
+		phys = <&usb2phy0_host>, <&combphy1 PHY_TYPE_USB3>;
+		phy-names = "usb2-phy", "usb3-phy";
+		phy_type = "utmi_wide";
+		power-domains = <&power RK3568_PD_PIPE>;
+		resets = <&cru SRST_USB3OTG1>;
+		snps,dis_u2_susphy_quirk;
+		status = "disabled";
+	};
+
 	gic: interrupt-controller@fd400000 {
 		compatible = "arm,gic-v3";
 		reg = <0x0 0xfd400000 0 0x10000>, /* GICD */
@@ -297,7 +331,6 @@  pmu_io_domains: io-domains {
 	};
 
 	pipegrf: syscon@fdc50000 {
-		compatible = "rockchip,rk3568-pipe-grf", "syscon";
 		reg = <0x0 0xfdc50000 0x0 0x1000>;
 	};